u32 flags;
};
-int
+static int
_nouveau_gpuobj_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
return 0;
}
-int
+static int
_nouveau_object_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
kfree(object);
}
-void
+static void
_nouveau_object_dtor(struct nouveau_object *object)
{
nouveau_object_destroy(object);
return 0;
}
-int
+static int
_nouveau_object_init(struct nouveau_object *object)
{
return nouveau_object_init(object);
return 0;
}
-int
+static int
_nouveau_object_fini(struct nouveau_object *object, bool suspend)
{
return nouveau_object_fini(object, suspend);
* Authors: Ben Skeggs
*/
-#include <core/os.h>
+#include <core/option.h>
#include <core/debug.h>
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
-u32 nva3_pcopy_data[] = {
+static u32 nva3_pcopy_data[] = {
/* 0x0000: ctx_object */
0x00000000,
/* 0x0004: ctx_dma */
0x00000800,
};
-u32 nva3_pcopy_code[] = {
+static u32 nva3_pcopy_code[] = {
/* 0x0000: main */
0x04fe04bd,
0x3517f000,
-u32 nvc0_pcopy_data[] = {
+static u32 nvc0_pcopy_data[] = {
/* 0x0000: ctx_object */
0x00000000,
/* 0x0004: ctx_query_address_high */
0x00000800,
};
-u32 nvc0_pcopy_code[] = {
+static u32 nvc0_pcopy_code[] = {
/* 0x0000: main */
0x04fe04bd,
0x3517f000,
-uint32_t nv98_pcrypt_data[] = {
+static uint32_t nv98_pcrypt_data[] = {
/* 0x0000: ctx_dma */
/* 0x0000: ctx_dma_query */
0x00000000,
0x00000000,
};
-uint32_t nv98_pcrypt_code[] = {
+static uint32_t nv98_pcrypt_code[] = {
0x17f004bd,
0x0010fe35,
0xf10004fe,
#include <core/subdev.h>
#include <core/device.h>
+#include <subdev/vga.h>
u8
nv_rdport(void *obj, int head, u16 port)
iowrite32_native(data, chan->user + addr);
}
-int
+static int
nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
{
int engidx = nv_hclass(priv) & 0xff;
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
-int
+static int
nv84_fifo_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
-uint32_t nvc0_grgpc_data[] = {
+static uint32_t nvc0_grgpc_data[] = {
0x00000000,
0x00000000,
0x00000000,
0x08000750,
};
-uint32_t nvc0_grgpc_code[] = {
+static uint32_t nvc0_grgpc_code[] = {
0x03060ef5,
0x9800d898,
0x86f001d9,
-uint32_t nvc0_grhub_data[] = {
+static uint32_t nvc0_grhub_data[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
-uint32_t nvc0_grhub_code[] = {
+static uint32_t nvc0_grhub_code[] = {
0x03090ef5,
0x9800d898,
0x86f001d9,
return 0;
}
-struct nouveau_ofuncs
+static struct nouveau_ofuncs
nv40_graph_ofuncs = {
.ctor = nv40_graph_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
return 0;
}
-struct nouveau_ofuncs
+static struct nouveau_ofuncs
nv50_graph_ofuncs = {
.ctor = nv50_graph_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
return 0;
}
-struct nouveau_ofuncs
+static struct nouveau_ofuncs
nv31_mpeg_ofuncs = {
.ctor = nv31_mpeg_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
.wr32 = _nouveau_gpuobj_wr32,
};
-struct nouveau_omthds
+static struct nouveau_omthds
nv31_mpeg_omthds[] = {
{ 0x0190, nv31_mpeg_mthd_dma },
{ 0x01a0, nv31_mpeg_mthd_dma },
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
+#include <subdev/bios/conn.h>
u16
dcb_conntab(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
}
#endif
-struct mxm_shadow_h {
+static struct mxm_shadow_h {
const char *name;
bool (*exec)(struct nouveau_mxm *, u8 version);
} _mxm_shadow[] = {
spinlock_t lock;
};
-void
+static void
nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
struct nouveau_gpuobj *pgt[2])
{
return phys;
}
-void
+static void
nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
}
}
-void
+static void
nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
}
}
-void
+static void
nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
{
pte <<= 3;
}
}
-void
+static void
nv50_vm_flush(struct nouveau_vm *vm)
{
struct nouveau_engine *engine;
spinlock_t lock;
};
-void
+static void
nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
struct nouveau_gpuobj *pgt[2])
{
return phys;
}
-void
+static void
nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
}
}
-void
+static void
nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
}
}
-void
+static void
nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
{
pte <<= 3;
spin_unlock_irqrestore(&priv->lock, flags);
}
-void
+static void
nvc0_vm_flush(struct nouveau_vm *vm)
{
struct nouveau_vm_pgd *vpgd;
return 0;
}
-int
+static int
nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli,
u32 parent, u32 handle, u32 engine,
struct nouveau_channel **pchan)
nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}
-bool
+static bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
struct dp_train_func *func)
{
module_param_named(noaccel, nouveau_noaccel, int, 0400);
MODULE_PARM_DESC(modeset, "enable driver");
-int nouveau_modeset = -1;
+static int nouveau_modeset = -1;
module_param_named(modeset, nouveau_modeset, int, 0400);
static struct drm_driver driver;
return 0;
}
-int
+static int
nouveau_drm_load(struct drm_device *dev, unsigned long flags)
{
struct pci_dev *pdev = dev->pdev;
return ret;
}
-int
+static int
nouveau_drm_unload(struct drm_device *dev)
{
struct nouveau_drm *drm = nouveau_drm(dev);
return 0;
}
-int
+static int
nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
{
struct pci_dev *pdev = dev->pdev;
return 0;
}
-void
+static void
nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
{
struct nouveau_cli *cli = nouveau_cli(fpriv);
mutex_unlock(&drm->client.mutex);
}
-void
+static void
nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
{
struct nouveau_cli *cli = nouveau_cli(fpriv);
#include <subdev/mc.h>
#include "nouveau_drm.h"
+#include "nouveau_irq.h"
#include "nv50_display.h"
void
return 0;
}
-uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
+static const uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
static int
return 0;
}
-uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
+static const uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
-uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
+static const uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
static int
return 0;
}
-void
+static void
nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
struct nouveau_mm *mm = man->priv;
return 0;
}
-void
+static void
nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}
return 0;
}
-void
+static void
nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}
#include "nouveau_drm.h"
#include "nouveau_acpi.h"
#include "nouveau_fbcon.h"
+#include "nouveau_vga.h"
static unsigned int
nouveau_vga_set_decode(void *priv, bool state)