ath9k_hw: update EEPROM data structure for AR9280
authorFelix Fietkau <nbd@openwrt.org>
Mon, 26 Apr 2010 19:04:34 +0000 (15:04 -0400)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 27 Apr 2010 20:09:17 +0000 (16:09 -0400)
Adds read access for the 5 GHz fast clock flag

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/eeprom.h
drivers/net/wireless/ath/ath9k/eeprom_def.c

index fb9c8c92eabeb79fde04c928f977cb16de882aae..21354c15a9a9b1181fd2eaa6d7933c5706019b47 100644 (file)
@@ -300,7 +300,8 @@ struct base_eep_header {
        u32 binBuildNumber;
        u8 deviceType;
        u8 pwdclkind;
-       u8 futureBase_1[2];
+       u8 fastClk5g;
+       u8 divChain;
        u8 rxGainType;
        u8 dacHiPwrMode_5G;
        u8 openLoopPwrCntl;
index cf59799ef3073553673e938c96e80be22556a1ee..e591ad6016e58ad215f6c27dd2916a7a4e60bfaf 100644 (file)
@@ -274,6 +274,8 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
                return pBase->txMask;
        case EEP_RX_MASK:
                return pBase->rxMask;
+       case EEP_FSTCLK_5G:
+               return pBase->fastClk5g;
        case EEP_RXGAIN_TYPE:
                return pBase->rxGainType;
        case EEP_TXGAIN_TYPE: