powerpc/8xx: Implementation of PAGE_EXEC

This patch implements PAGE_EXEC capability on the 8xx.

All pages PP exec bits are set to 000, which means Execute for
Supervisor and no Execute for User.
Then we use the APG to say whether accesses are according to Page
rules, "all Supervisor" rules (Exec for all) and
"all User" rules (Exec for noone)

Therefore, we define 4 APG groups. msb is _PAGE_EXEC,
lsb is _PAGE_USER. MI_AP is initialised as follows:
GP0 (00) => Not User, no exec => 11 (all accesses performed as user)
GP1 (01) => User but no exec => 11 (all accesses performed as user)
GP2 (10) => Not User, exec => 01 (rights according to page definition)
GP3 (11) => User, exec => 00 (all accesses performed as supervisor)

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[scottwood: comments: s/exec/data/ on data side, and s/pages/pages'/]
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 6367b8347dad9b0bceb3507573450b2e7c672400..ae1fa65bb26d68264226104e90a41c3c0bb67bfe 100644 (file)
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -366,7 +366,7 @@ enum {
            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 #define CPU_FTRS_CLASSIC32     (CPU_FTR_COMMON | CPU_FTR_USE_TB)
-#define CPU_FTRS_8XX   (CPU_FTR_USE_TB)
+#define CPU_FTRS_8XX   (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_40X   (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_44X   (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \

diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
index d41200c01d8547b3e80c2bfb420127d6a688342a..f05500a29a60d6f23f4e23de99821995511ccae0 100644 (file)
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -27,6 +27,19 @@
 #define MI_Ks          0x80000000      /* Should not be set */
 #define MI_Kp          0x40000000      /* Should always be set */
 
+/*
+ * All pages' PP exec bits are set to 000, which means Execute for Supervisor
+ * and no Execute for User.
+ * Then we use the APG to say whether accesses are according to Page rules,
+ * "all Supervisor" rules (Exec for all) and "all User" rules (Exec for noone)
+ * Therefore, we define 4 APG groups. msb is _PAGE_EXEC, lsb is _PAGE_USER
+ * 0 (00) => Not User, no exec => 11 (all accesses performed as user)
+ * 1 (01) => User but no exec => 11 (all accesses performed as user)
+ * 2 (10) => Not User, exec => 01 (rights according to page definition)
+ * 3 (11) => User, exec => 00 (all accesses performed as supervisor)
+ */
+#define MI_APG_INIT    0xf4ffffff
+
 /* The effective page number register.  When read, contains the information
  * about the last instruction TLB miss.  When MI_RPN is written, bits in
  * this register are used to create the TLB entry.
@@ -87,6 +100,19 @@
 #define MD_Ks          0x80000000      /* Should not be set */
 #define MD_Kp          0x40000000      /* Should always be set */
 
+/*
+ * All pages' PP data bits are set to either 000 or 011, which means
+ * respectively RW for Supervisor and no access for User, or RO for
+ * Supervisor and no access for user.
+ * Then we use the APG to say whether accesses are according to Page rules or
+ * "all Supervisor" rules (Access to all)
+ * Therefore, we define 2 APG groups. lsb is _PAGE_USER
+ * 0 => No user => 01 (all accesses performed according to page definition)
+ * 1 => User => 00 (all accesses performed as supervisor
+ *                                 according to page definition)
+ */
+#define MD_APG_INIT    0x4fffffff
+
 /* The effective page number register.  When read, contains the information
  * about the last instruction TLB miss.  When MD_RPN is written, bits in
  * this register are used to create the TLB entry.

diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index b82094e4c24253a95824b76a4587193cd4d1fa7e..a0e2ba9609760e4108ce9aca0a4fd255fa15b1d1 100644 (file)
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -39,8 +39,9 @@
  */
 #define _PAGE_GUARDED  0x0010  /* Copied to L1 G entry in DTLB */
 #define _PAGE_USER     0x0020  /* Copied to L1 APG lsb */
-#define _PAGE_ACCESSED 0x0040  /* software: page referenced */
+#define _PAGE_EXEC     0x0040  /* Copied to L1 APG */
 #define _PAGE_WRITETHRU        0x0080  /* software: caching is write through */
+#define _PAGE_ACCESSED 0x0800  /* software: page referenced */
 
 #define _PAGE_RO       0x0600  /* Supervisor RO, User no access */
 

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index c79184d86f58464d7b0b8edd166c62a4a4d05d94..78c1eba4c04a432ea233983e81d9da7a87071834 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -357,7 +357,7 @@ InstructionTLBMiss:
        lwz     r10, 0(r10)     /* Get the pte */
 
        /* Insert the APG into the TWC from the Linux PTE. */
-       rlwimi  r11, r10, 0, 26, 26
+       rlwimi  r11, r10, 0, 25, 26
        /* Load the MI_TWC with the attributes for this "segment." */
        MTSPR_CPU6(SPRN_MI_TWC, r11, r3)        /* Set segment attributes */
 
@@ -449,6 +449,7 @@ DataStoreTLBMiss:
         */
        li      r11, RPN_PATTERN
        rlwimi  r10, r11, 0, 24, 28     /* Set 24-27, clear 28 */
+       rlwimi  r10, r11, 0, 20, 20     /* clear 20 */
        MTSPR_CPU6(SPRN_MD_RPN, r10, r3)        /* Update TLB entry */
 
        /* Restore registers */
@@ -769,15 +770,20 @@ initial_mmu:
        ori     r8, r8, MI_EVALID       /* Mark it valid */
        mtspr   SPRN_MI_EPN, r8
        mtspr   SPRN_MD_EPN, r8
-       li      r8, MI_PS8MEG           /* Set 8M byte page */
+       li      r8, MI_PS8MEG | (2 << 5)        /* Set 8M byte page, APG 2 */
        ori     r8, r8, MI_SVALID       /* Make it valid */
        mtspr   SPRN_MI_TWC, r8
+       li      r8, MI_PS8MEG           /* Set 8M byte page, APG 0 */
+       ori     r8, r8, MI_SVALID       /* Make it valid */
        mtspr   SPRN_MD_TWC, r8
        li      r8, MI_BOOTINIT         /* Create RPN for address 0 */
        mtspr   SPRN_MI_RPN, r8         /* Store TLB entry */
        mtspr   SPRN_MD_RPN, r8
-       lis     r8, MI_Kp@h             /* Set the protection mode */
+       lis     r8, MI_APG_INIT@h       /* Set protection modes */
+       ori     r8, r8, MI_APG_INIT@l
        mtspr   SPRN_MI_AP, r8
+       lis     r8, MD_APG_INIT@h
+       ori     r8, r8, MD_APG_INIT@l
        mtspr   SPRN_MD_AP, r8
 
        /* Map another 8 MByte at the IMMR to get the processor