projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 40306c8)
arm: mach-mv78xx0: use plus instead of or for address definitions
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 11 Sep 2012 12:27:16 +0000 (14:27 +0200)
committerJason Cooper <jason@lakedaemon.net>
Fri, 21 Sep 2012 18:03:04 +0000 (18:03 +0000)
Since we are going to use IOMEM() to define many base virtual
addresses, we can no longer use binary or to define the individual
register addresses ("binary or" arithmetic on pointers is not
allowed). Instead, use the more conventional plus operator to do so.

The binary or operators were actually not useful because the low-order
bits of the base address were always zero, so the usage of the binary
or operators was effectively identical to a plus operator.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h patch | blob | blame | history
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h patch | blob | blame | history

diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059bdbb1459b2ae21d69b6050176cba2..5f03484584d4e1aed603b3df15cf23b7cbced792 100644 (file)
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
 
 #include <mach/mv78xx0.h>
 
-#define CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL            (BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH                0x00020000
 
-#define RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK           (BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN      0x00000004
 
-#define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET             0x00000001
 
 #define BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
-#define IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF      0x0000
 #define IRQ_CAUSE_LOW_OFF      0x0004
 #define IRQ_CAUSE_HIGH_OFF     0x0008
@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF       0x0010
 #define IRQ_MASK_HIGH_OFF      0x0014
 
-#define TIMER_VIRT_BASE                (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE                (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE                (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE                (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c52a0b6331a4e02146f71edc127d95cb7f..a86e79ecfeafc01c14a4891d39c15c1937a29257 100644 (file)
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -65,47 +65,47 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE          (MV78XX0_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU0_BASE  (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE  (DDR_VIRT_BASE | 0x1570)
-
-#define DEV_BUS_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE      (MV78XX0_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET_LOW   (DEV_BUS_VIRT_BASE | 0x0030)
-#define  SAMPLE_AT_RESET_HIGH  (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_VIRT_BASE                (DEV_BUS_VIRT_BASE | 0x0100)
-#define  I2C_0_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x1000)
-#define  I2C_1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x1100)
-#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
-#define  UART2_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2200)
-#define  UART2_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2200)
-#define  UART3_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2300)
-#define  UART3_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2300)
-
-#define GE10_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x30000)
-#define GE11_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x34000)
-
-#define PCIE00_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x40000)
-#define PCIE01_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x44000)
-#define PCIE02_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x48000)
-#define PCIE03_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x4c000)
-
-#define USB0_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x50000)
-#define USB1_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x51000)
-#define USB2_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x52000)
-
-#define GE00_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x74000)
-
-#define PCIE10_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x80000)
-#define PCIE11_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x84000)
-#define PCIE12_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x88000)
-#define PCIE13_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x8c000)
-
-#define SATA_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define DDR_VIRT_BASE          (MV78XX0_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU0_BASE  (DDR_VIRT_BASE + 0x1500)
+#define  DDR_WINDOW_CPU1_BASE  (DDR_VIRT_BASE + 0x1570)
+
+#define DEV_BUS_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE      (MV78XX0_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET_LOW   (DEV_BUS_VIRT_BASE + 0x0030)
+#define  SAMPLE_AT_RESET_HIGH  (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_VIRT_BASE                (DEV_BUS_VIRT_BASE + 0x0100)
+#define  I2C_0_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x1000)
+#define  I2C_1_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x1100)
+#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE + 0x2100)
+#define  UART2_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x2200)
+#define  UART2_VIRT_BASE       (DEV_BUS_VIRT_BASE + 0x2200)
+#define  UART3_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x2300)
+#define  UART3_VIRT_BASE       (DEV_BUS_VIRT_BASE + 0x2300)
+
+#define GE10_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x30000)
+#define GE11_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x34000)
+
+#define PCIE00_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x40000)
+#define PCIE01_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x44000)
+#define PCIE02_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x48000)
+#define PCIE03_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x4c000)
+
+#define USB0_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x50000)
+#define USB1_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x51000)
+#define USB2_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x52000)
+
+#define GE00_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0x74000)
+
+#define PCIE10_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x80000)
+#define PCIE11_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x84000)
+#define PCIE12_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x88000)
+#define PCIE13_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x8c000)
+
+#define SATA_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE + 0xa0000)
 
 /*
  * Supported devices and revisions.