drm/i915/gvt: Fix PTE write flush for taking runtime pm properly

Make sure to take runtime pm when write PTE flush which ensure to
write to hw properly. This fixes warning during mdev/vgpu creation
which will do ggtt reset.

------------[ cut here ]------------
WARNING: CPU: 1 PID: 9375 at drivers/gpu/drm/i915/intel_drv.h:1748 fwtable_write32+0x1c2/0x1e0 [i915]
 RPM wakelock ref not held during HW access
Call Trace:
  ? dump_stack+0x5c/0x81
  ? __warn+0xbe/0xe0
  ? warn_slowpath_fmt+0x5a/0x80
  ? wake_up_klogd+0x37/0x40
  ? vprintk_emit+0x2ef/0x370
  ? fwtable_write32+0x1c2/0x1e0 [i915]
  ? gtt_set_entry64+0xbb/0xd0 [i915]
  ? intel_vgpu_reset_ggtt+0x88/0xf0 [i915]
  ? intel_vgpu_init_gtt+0xa5/0x4f0 [i915]
  ? intel_gvt_create_vgpu+0x1b5/0x250 [i915]
  ? kobject_put+0x1b/0x50
  ? intel_vgpu_create+0x4e/0x130 [kvmgt]
  ? mdev_device_create+0x186/0x2a0 [mdev]
  ? create_store+0xba/0xe0 [mdev]
  ? create_store+0xba/0xe0 [mdev]
  ? kernfs_fop_write+0x109/0x1a0
  ? kernfs_fop_write+0x109/0x1a0
  ? __vfs_write+0x33/0x160
  ? __fput+0x161/0x1d0
  ? vfs_write+0xb0/0x190
  ? SyS_write+0x52/0xc0
  ? exit_to_usermode_loop+0x7a/0xa0
  ? entry_SYSCALL_64_fastpath+0x1e/0xad

v2: remove unrelated oops info

v3: change to take runtime pm for ggtt reset instead of get/put for
    each pte write flush

Fixes: d650ac060237 ("drm/i915/gvt: reset the GGTT entry when vGPU created")
Cc: Ping Gao <ping.a.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 69d3d8ddecc25846cb47d064f2d165a54526fac5..acbe3f2ad6fc5b019b9f0fa10ee2f8ac4874cf6a 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2290,12 +2290,15 @@ void intel_gvt_clean_gtt(struct intel_gvt *gvt)
 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu)
 {
        struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
        struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
        u32 index;
        u32 offset;
        u32 num_entries;
        struct intel_gvt_gtt_entry e;
 
+       intel_runtime_pm_get(dev_priv);
+
        memset(&e, 0, sizeof(struct intel_gvt_gtt_entry));
        e.type = GTT_TYPE_GGTT_PTE;
        ops->set_pfn(&e, gvt->gtt.scratch_ggtt_mfn);
@@ -2310,6 +2313,8 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu)
        num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
        for (offset = 0; offset < num_entries; offset++)
                ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);
+
+       intel_runtime_pm_put(dev_priv);
 }
 
 /**