clk: tegra: add FUSE clock device
authorAlexandre Courbot <acourbot@nvidia.com>
Thu, 21 Nov 2013 02:38:10 +0000 (03:38 +0100)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Tue, 26 Nov 2013 16:46:57 +0000 (18:46 +0200)
This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drivers/clk/tegra/clk-tegra114.c
drivers/clk/tegra/clk-tegra124.c
drivers/clk/tegra/clk-tegra20.c
drivers/clk/tegra/clk-tegra30.c

index 875859d9ab5f119d1e316910d4a1476217e9c638..2a1b0b82462a1ab2af866bed367b054f03868b23 100644 (file)
@@ -918,6 +918,7 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
        { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
        { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
+       { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
        { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
        { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
 };
index 8af9d3929016d329ae52d596da773e2abb628383..0ef4485e9b0adda582603325da9ba0f51718ad7f 100644 (file)
@@ -1009,6 +1009,7 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
        { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
        { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
+       { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
        { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
        { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
 };
index be5bdbab78a6d0c4292a7b3b1a307161548c7b5a..b3b7204acfe78d35a9ca9172665222b316920bc7 100644 (file)
@@ -446,6 +446,7 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
        { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
        { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
+       { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
        { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
        { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
        { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
index 3afa09761bb370fadc7fedcaa1678ec35cb1a8f8..dcb6843b3a89bec1eb542bf963a2622f9b36df6b 100644 (file)
@@ -650,7 +650,7 @@ static struct tegra_devclk devclks[] __initdata = {
        { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
        { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
        { .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
-       { .con_id = "fuse", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE },
+       { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
        { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
        { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
        { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },