ARM: dts: i.MX6: configure L2 cache data and tag latency

Configure the data and tag latency for the L2 cache. This improves the
system performance.

This configuration is taken from Freescale's kernel patch

"ENGR00153601 [MX6]Adjust L2 cache parameter" [1]

which does

writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));

In this patch we are doing the same via the device tree.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9e8296e4c3434afdf61004e62e2af83c9bbc8490..fd7cc6d18f36ca691dfdc1bcb6d43c0ea52fc96f 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -106,6 +106,8 @@
                        interrupts = <0 92 0x04>;
                        cache-unified;
                        cache-level = <2>;
+                       arm,tag-latency = <4 2 3>;
+                       arm,data-latency = <4 2 3>;
                };
 
                pmu {