clk: tegra: Add SATA seq input control
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Wed, 15 Mar 2017 15:42:05 +0000 (17:42 +0200)
committerThierry Reding <treding@nvidia.com>
Mon, 20 Mar 2017 13:26:03 +0000 (14:26 +0100)
This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c
include/linux/clk/tegra.h

index 6f29125ec4391460f61a1fa3b1b9f037ff3909be..f3e51e640d4df3221efd5469f433559cae83e83d 100644 (file)
 #define SATA_PLL_CFG0                          0x490
 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL       BIT(0)
 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET       BIT(2)
+#define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL                BIT(4)
+#define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE       BIT(5)
+#define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE     BIT(6)
+#define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE   BIT(7)
+
 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ                BIT(13)
 #define SATA_PLL_CFG0_SEQ_ENABLE               BIT(24)
 
@@ -483,6 +488,26 @@ void tegra210_sata_pll_hw_sequence_start(void)
 }
 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
 
+void tegra210_set_sata_pll_seq_sw(bool state)
+{
+       u32 val;
+
+       val = readl_relaxed(clk_base + SATA_PLL_CFG0);
+       if (state) {
+               val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
+               val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
+               val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
+               val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
+       } else {
+               val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
+               val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
+               val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
+               val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
+       }
+       writel_relaxed(val, clk_base + SATA_PLL_CFG0);
+}
+EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
+
 static inline void _pll_misc_chk_default(void __iomem *base,
                                        struct tegra_clk_pll_params *params,
                                        u8 misc_num, u32 default_val, u32 mask)
index e17d32831e2846d0b6055ec35694917c5753c012..d23c9cf26993b5f4518710c2495f426cb48abf85 100644 (file)
@@ -125,6 +125,7 @@ extern void tegra210_xusb_pll_hw_control_enable(void);
 extern void tegra210_xusb_pll_hw_sequence_start(void);
 extern void tegra210_sata_pll_hw_control_enable(void);
 extern void tegra210_sata_pll_hw_sequence_start(void);
+extern void tegra210_set_sata_pll_seq_sw(bool state);
 extern void tegra210_put_utmipll_in_iddq(void);
 extern void tegra210_put_utmipll_out_iddq(void);