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microblaze: Define correct L1_CACHE_SHIFT value
authorMichal Simek <monstr@monstr.eu>
Mon, 26 Apr 2010 11:43:23 +0000 (13:43 +0200)
committerMichal Simek <monstr@monstr.eu>
Thu, 6 May 2010 09:21:59 +0000 (11:21 +0200)
Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>
arch/microblaze/include/asm/cache.h patch | blob | blame | history

diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
index e52210891d78ed167a71e24ca35c1cd9abee6bf4..4efe96a036f74a7ce058f563d44c21f46c0cc374 100644 (file)
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -15,7 +15,7 @@
 
 #include <asm/registers.h>
 
-#define L1_CACHE_SHIFT 2
+#define L1_CACHE_SHIFT 5
 /* word-granular cache in microblaze */
 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)