ARM: at91: sama5d3: reduce TWI internal clock frequency

With some devices, transfer hangs during I2C frame transmission. This issue
disappears when reducing the internal frequency of the TWI IP. Even if it is
indicated that internal clock max frequency is 66MHz, it seems we have
oversampling on I2C signals making TWI believe that a transfer in progress
is done.

This fix has no impact on the I2C bus frequency.

Cc: <stable@vger.kernel.org> #3.10+
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 3ea86428ee0964f11d0955a90d0348626e68da58..a28873fe30491334e9feaad188901bea37d34d24 100644 (file)
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -95,19 +95,19 @@ static struct clk twi0_clk = {
        .name           = "twi0_clk",
        .pid            = SAMA5D3_ID_TWI0,
        .type           = CLK_TYPE_PERIPHERAL,
-       .div            = AT91_PMC_PCR_DIV2,
+       .div            = AT91_PMC_PCR_DIV8,
 };
 static struct clk twi1_clk = {
        .name           = "twi1_clk",
        .pid            = SAMA5D3_ID_TWI1,
        .type           = CLK_TYPE_PERIPHERAL,
-       .div            = AT91_PMC_PCR_DIV2,
+       .div            = AT91_PMC_PCR_DIV8,
 };
 static struct clk twi2_clk = {
        .name           = "twi2_clk",
        .pid            = SAMA5D3_ID_TWI2,
        .type           = CLK_TYPE_PERIPHERAL,
-       .div            = AT91_PMC_PCR_DIV2,
+       .div            = AT91_PMC_PCR_DIV8,
 };
 static struct clk mmc0_clk = {
        .name           = "mci0_clk",