Merge branch 'clksrc' into devel
authorRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 5 Jan 2011 18:09:03 +0000 (18:09 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 5 Jan 2011 18:09:03 +0000 (18:09 +0000)
Conflicts:
arch/arm/mach-vexpress/v2m.c
arch/arm/plat-omap/counter_32k.c
arch/arm/plat-versatile/Makefile

12 files changed:
1  2 
arch/arm/Kconfig
arch/arm/common/timer-sp.c
arch/arm/include/asm/system.h
arch/arm/kernel/entry-common.S
arch/arm/kernel/smp.c
arch/arm/mach-realview/core.c
arch/arm/mach-sa1100/generic.c
arch/arm/mach-versatile/core.c
arch/arm/mach-vexpress/v2m.c
arch/arm/plat-iop/time.c
arch/arm/plat-omap/counter_32k.c
arch/arm/plat-versatile/Makefile

Simple merge
index 4740313daa5b0eed4cd2d432903b5f25efda2a83,0000000000000000000000000000000000000000..6ef3342153b90c003d43a12123eee18560efffc7
mode 100644,000000..100644
--- /dev/null
@@@ -1,154 -1,0 +1,152 @@@
-       .shift          = 20,
 +/*
 + *  linux/arch/arm/common/timer-sp.c
 + *
 + *  Copyright (C) 1999 - 2003 ARM Limited
 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 + */
 +#include <linux/clocksource.h>
 +#include <linux/clockchips.h>
 +#include <linux/interrupt.h>
 +#include <linux/irq.h>
 +#include <linux/io.h>
 +
 +#include <asm/hardware/arm_timer.h>
 +
 +/*
 + * These timers are currently always setup to be clocked at 1MHz.
 + */
 +#define TIMER_FREQ_KHZ        (1000)
 +#define TIMER_RELOAD  (TIMER_FREQ_KHZ * 1000 / HZ)
 +
 +static void __iomem *clksrc_base;
 +
 +static cycle_t sp804_read(struct clocksource *cs)
 +{
 +      return ~readl(clksrc_base + TIMER_VALUE);
 +}
 +
 +static struct clocksource clocksource_sp804 = {
 +      .name           = "timer3",
 +      .rating         = 200,
 +      .read           = sp804_read,
 +      .mask           = CLOCKSOURCE_MASK(32),
-       cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift);
-       clocksource_register(cs);
 +      .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 +};
 +
 +void __init sp804_clocksource_init(void __iomem *base)
 +{
 +      struct clocksource *cs = &clocksource_sp804;
 +
 +      clksrc_base = base;
 +
 +      /* setup timer 0 as free-running clocksource */
 +      writel(0, clksrc_base + TIMER_CTRL);
 +      writel(0xffffffff, clksrc_base + TIMER_LOAD);
 +      writel(0xffffffff, clksrc_base + TIMER_VALUE);
 +      writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 +              clksrc_base + TIMER_CTRL);
 +
++      clocksource_register_khz(cs, TIMER_FREQ_KHZ);
 +}
 +
 +
 +static void __iomem *clkevt_base;
 +
 +/*
 + * IRQ handler for the timer
 + */
 +static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
 +{
 +      struct clock_event_device *evt = dev_id;
 +
 +      /* clear the interrupt */
 +      writel(1, clkevt_base + TIMER_INTCLR);
 +
 +      evt->event_handler(evt);
 +
 +      return IRQ_HANDLED;
 +}
 +
 +static void sp804_set_mode(enum clock_event_mode mode,
 +      struct clock_event_device *evt)
 +{
 +      unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 +
 +      writel(ctrl, clkevt_base + TIMER_CTRL);
 +
 +      switch (mode) {
 +      case CLOCK_EVT_MODE_PERIODIC:
 +              writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
 +              ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 +              break;
 +
 +      case CLOCK_EVT_MODE_ONESHOT:
 +              /* period set, and timer enabled in 'next_event' hook */
 +              ctrl |= TIMER_CTRL_ONESHOT;
 +              break;
 +
 +      case CLOCK_EVT_MODE_UNUSED:
 +      case CLOCK_EVT_MODE_SHUTDOWN:
 +      default:
 +              break;
 +      }
 +
 +      writel(ctrl, clkevt_base + TIMER_CTRL);
 +}
 +
 +static int sp804_set_next_event(unsigned long next,
 +      struct clock_event_device *evt)
 +{
 +      unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 +
 +      writel(next, clkevt_base + TIMER_LOAD);
 +      writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 +
 +      return 0;
 +}
 +
 +static struct clock_event_device sp804_clockevent = {
 +      .name           = "timer0",
 +      .shift          = 32,
 +      .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 +      .set_mode       = sp804_set_mode,
 +      .set_next_event = sp804_set_next_event,
 +      .rating         = 300,
 +      .cpumask        = cpu_all_mask,
 +};
 +
 +static struct irqaction sp804_timer_irq = {
 +      .name           = "timer",
 +      .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 +      .handler        = sp804_timer_interrupt,
 +      .dev_id         = &sp804_clockevent,
 +};
 +
 +void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
 +{
 +      struct clock_event_device *evt = &sp804_clockevent;
 +
 +      clkevt_base = base;
 +
 +      evt->irq = timer_irq;
 +      evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
 +      evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
 +      evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 +
 +      setup_irq(timer_irq, &sp804_timer_irq);
 +      clockevents_register_device(evt);
 +}
Simple merge
Simple merge
Simple merge
index 14fbe50376b6888798f3821360d2175d1227944f,3d653e05b75d621186c1cccda457dc95a8490c01..aad806c5cb12058a2f9ff9f66004283a2a27c006
  #include <mach/clkdev.h>
  #include <mach/platform.h>
  #include <mach/irqs.h>
 -#include <plat/timer-sp.h>
 +#include <asm/hardware/timer-sp.h>
  
+ #include <plat/sched_clock.h>
  #include "core.h"
  
 -/* used by entry-macro.S and platsmp.c */
 -void __iomem *gic_cpu_base_addr;
 -
  #ifdef CONFIG_ZONE_DMA
  /*
   * Adjust the zones if there are restrictions for DMA access.
Simple merge
index 6b93bd60027129f8bc107cec157a58e4a308218b,56cdc2257424d7fd1e2b9e012ecb293b796a0dcd..40a024c71e4b56e5b48c4068b197ba67f131a6a0
  #include <mach/clkdev.h>
  #include <mach/hardware.h>
  #include <mach/platform.h>
 -#include <plat/timer-sp.h>
 +#include <asm/hardware/timer-sp.h>
  
+ #include <plat/sched_clock.h>
  #include "core.h"
  
  /*
index 91ff2e0df8569c235d22eeb720edfc144b49816b,8c283100a9a0c73232b7eaa4d8cd3b0ebc58f701..de13603dc028313966899de0154c1aa97fbaf394
  #include <asm/mach/map.h>
  #include <asm/mach/time.h>
  #include <asm/hardware/arm_timer.h>
++#include <asm/hardware/timer-sp.h>
  
  #include <mach/clkdev.h>
  #include <mach/motherboard.h>
  
- #include <asm/hardware/timer-sp.h>
+ #include <plat/sched_clock.h>
  
 -#include <plat/timer-sp.h>
 -
  #include "core.h"
  
  #define V2M_PA_CS0    0x40000000
index 558cdfaf76b6a22a4ff6ff3a5190263c662a3268,2db6e60d149deba6f1d6651ef4aa64f68cb69243..07f23bb42bed4c4d4a47cce31b018709fabe0a61
@@@ -17,8 -17,8 +17,9 @@@
  #include <linux/interrupt.h>
  #include <linux/time.h>
  #include <linux/init.h>
+ #include <linux/sched.h>
  #include <linux/timex.h>
 +#include <linux/sched.h>
  #include <linux/io.h>
  #include <linux/clocksource.h>
  #include <linux/clockchips.h>
index 8722a136f3a5bee844f5643dd195c95f077db666,1b558efbe7320ee2c9436893c2d402d9f667666e..ea4644021fb9c0867c2e4ca4bd4bcb118e863f80
  #include <linux/kernel.h>
  #include <linux/init.h>
  #include <linux/clk.h>
- #include <linux/io.h>
 +#include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/sched.h>
+ #include <asm/sched_clock.h>
  
  #include <plat/common.h>
  #include <plat/board.h>
@@@ -165,16 -181,16 +182,16 @@@ static int __init omap_init_clocksource
                        return -ENODEV;
  
                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
 -              if (sync_32k_ick)
 +              if (!IS_ERR(sync_32k_ick))
                        clk_enable(sync_32k_ick);
  
-               clocksource_32k.mult = clocksource_hz2mult(32768,
-                                           clocksource_32k.shift);
                offset_32k = clocksource_32k.read(&clocksource_32k);
  
-               if (clocksource_register(&clocksource_32k))
+               if (clocksource_register_hz(&clocksource_32k, 32768))
                        printk(err, clocksource_32k.name);
+               init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
+                                      32768, SC_MULT, SC_SHIFT);
        }
        return 0;
  }
index aaa571d17924fc4085fb43e29f587f5026c4d472,8bb6ba6d3572b28ad64c075be7a6410f225a6e05..16dde08199349b4a004ab58746f43d40d0d88424
@@@ -1,6 -1,8 +1,7 @@@
  obj-y := clock.o
- obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
- obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
 -obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
+ ifneq ($(CONFIG_ARCH_INTEGRATOR),y)
+ obj-y += sched-clock.o
+ endif
  ifeq ($(CONFIG_LEDS_CLASS),y)
  obj-$(CONFIG_ARCH_REALVIEW) += leds.o
  obj-$(CONFIG_ARCH_VERSATILE) += leds.o