drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index fa7a6ca34cd654bb7c66665c4c80235b28ea2673..636d72f7dd42c3b160ec0f3b0e3eda045edbba29 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 
        dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 
+       if (intel_dsi->dual_link)
+               dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
+
        DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
                      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);