ARM: STi: DT: STiH407: 407 DT Entry for clockgen A0

Patch adds DT entries for clockgen A0

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 800f46f009f3838c98beaa83d05dd442acb68690..1bfa6799d7c5543837d6afa07e7cc77bc8878339 100644 (file)
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -7,6 +7,10 @@
  */
 / {
        clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
                /*
                 * Fixed 30MHz oscillator inputs to SoC
                 */
@@ -35,5 +39,30 @@
                        clock-frequency = <200000000>;
                        clock-output-names = "clk-s-icn-reg-0";
                };
+
+               clockgen-a@090ff000 {
+                       compatible = "st,clkgen-c32";
+                       reg = <0x90ff000 0x1000>;
+
+                       clk_s_a0_pll: clk-s-a0-pll {
+                               #clock-cells = <1>;
+                               compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+
+                               clocks = <&clk_sysin>;
+
+                               clock-output-names = "clk-s-a0-pll-ofd-0";
+                       };
+
+                       clk_s_a0_flexgen: clk-s-a0-flexgen {
+                               compatible = "st,flexgen";
+
+                               #clock-cells = <1>;
+
+                               clocks = <&clk_s_a0_pll 0>,
+                                        <&clk_sysin>;
+
+                               clock-output-names = "clk-ic-lmi0";
+                       };
+               };
        };
 };