regs->addr_cmap = ir & 0x0f;
}
+static inline void bt455_reset_reg(struct bt455_regs *regs)
+{
+ mb();
+ regs->addr_clr = 0;
+}
+
/*
* Read/write to a Bt455 color map register.
*/
-static inline void bt455_read_cmap_entry(struct bt455_regs *regs,
- int cr, u8 *grey)
+static inline void bt455_read_cmap_next(struct bt455_regs *regs, u8 *grey)
{
- bt455_select_reg(regs, cr);
mb();
regs->addr_cmap_data;
rmb();
regs->addr_cmap_data;
}
-static inline void bt455_write_cmap_entry(struct bt455_regs *regs,
- int cr, u8 grey)
+static inline void bt455_write_cmap_next(struct bt455_regs *regs, u8 grey)
{
- bt455_select_reg(regs, cr);
wmb();
regs->addr_cmap_data = 0x0;
wmb();
regs->addr_cmap_data = 0x0;
}
-static inline void bt455_write_ovly_entry(struct bt455_regs *regs,
- int cr, u8 grey)
+static inline void bt455_write_ovly_next(struct bt455_regs *regs, u8 grey)
{
- bt455_select_reg(regs, cr);
wmb();
regs->addr_ovly = 0x0;
wmb();
wmb();
regs->addr_ovly = 0x0;
}
+
+static inline void bt455_read_cmap_entry(struct bt455_regs *regs,
+ int cr, u8 *grey)
+{
+ bt455_select_reg(regs, cr);
+ bt455_read_cmap_next(regs, grey);
+}
+
+static inline void bt455_write_cmap_entry(struct bt455_regs *regs,
+ int cr, u8 grey)
+{
+ bt455_select_reg(regs, cr);
+ bt455_write_cmap_next(regs, grey);
+}
+
+static inline void bt455_write_ovly_entry(struct bt455_regs *regs, u8 grey)
+{
+ bt455_reset_reg(regs);
+ bt455_write_ovly_next(regs, grey);
+}
u8 bg = cursor->image.bg_color ? 0xf : 0x0;
bt455_write_cmap_entry(par->bt455, 8, bg);
- bt455_write_cmap_entry(par->bt455, 9, bg);
- bt455_write_ovly_entry(par->bt455, 0, fg);
+ bt455_write_cmap_next(par->bt455, bg);
+ bt455_write_ovly_next(par->bt455, fg);
}
if (cursor->set & (FB_CUR_SETSIZE | FB_CUR_SETSHAPE | FB_CUR_SETIMAGE))
bt431_set_cursor(par->bt431,
/* Init colormap. */
bt455_write_cmap_entry(par->bt455, 0, 0x0);
- bt455_write_cmap_entry(par->bt455, 1, 0xf);
+ bt455_write_cmap_next(par->bt455, 0xf);
/* Init hardware cursor. */
bt431_erase_cursor(par->bt431);