#define PCI9118_AI_CFG_PM (1 << 2) /* 1=post trigger */
#define PCI9118_AI_CFG_AM (1 << 1) /* 1=about trigger */
#define PCI9118_AI_CFG_START (1 << 0) /* 1=trigger start */
+#define PCI9118_FIFO_RESET_REG 0x34
-#define PCI9118_DELFIFO 0x34 /* W: A/D data FIFO reset */
#define PCI9118_INTSRC 0x38 /* R: interrupt reason register */
#define PCI9118_INTCTRL 0x38 /* W: interrupt control register */
outl(val, dev->iobase + PCI9118_TIMER_CTRL_REG);
}
+static void pci9118_ai_reset_fifo(struct comedi_device *dev)
+{
+ /* writing any value resets the A/D FIFO */
+ outl(0, dev->iobase + PCI9118_FIFO_RESET_REG);
+}
+
static int check_channel_list(struct comedi_device *dev,
struct comedi_subdevice *s, int n_chan,
unsigned int *chanlist, int frontadd, int backadd)
if (!setup_channel_list(dev, s, 1, &insn->chanspec, 0, 0, 0, 0))
return -EINVAL;
- outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
+ pci9118_ai_reset_fifo(dev);
for (n = 0; n < insn->n; n++) {
pci9118_ai_start_conv(dev);
ret = comedi_timeout(dev, s, insn, pci9118_ai_eoc, 0);
if (ret) {
- outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
+ pci9118_ai_reset_fifo(dev);
return ret;
}
data[n] = (val >> 4) & 0xfff;
}
- outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
+ pci9118_ai_reset_fifo(dev);
return n;
}
/* reset scan queue */
outl(1, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
outl(2, dev->iobase + PCI9118_AI_AUTOSCAN_MODE_REG);
- outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
+ pci9118_ai_reset_fifo(dev);
devpriv->ai_do = 0;
devpriv->usedma = 0;
*/
outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_AI_CFG_REG);
udelay(1);
- outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
+ pci9118_ai_reset_fifo(dev);
/* clear A/D and INT status registers */
inl(dev->iobase + PCI9118_AI_STATUS_REG);
outl(0, dev->iobase + PCI9118_DIO_REG); /* reset digi outs to L */
udelay(10);
inl(dev->iobase + PCI9118_AI_FIFO_REG);
- outl(0, dev->iobase + PCI9118_DELFIFO); /* flush FIFO */
+ pci9118_ai_reset_fifo(dev);
outl(0, dev->iobase + PCI9118_INTSRC); /* remove INT requests */
/* clear A/D and INT status registers */
inl(dev->iobase + PCI9118_AI_STATUS_REG);