mfd: dbx500: Remove any mention of the BML8580CLK

The platform which it pertains to is no longer supported and is actually
causing some confusion in the new common clock implementation. A recent
patch removed its use in the clock driver, let's take out the definitions
too.

Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 53f371dcbb6e96550537b108fffbba1c00af3015..b9ce60c301de026bba38daf276e83773c44379ec 100644 (file)
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -480,7 +480,6 @@ static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
        CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
        CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
        CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
-       CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
        CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
        CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
        CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),

diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 4f6f0fa5d3b7768d4265b632f4e1620be22c347b..7cc32a8ff01c01b06e8d29ae44134253d81828ba 100644 (file)
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -32,7 +32,6 @@
 #define PRCM_PER7CLK_MGT       (0x040)
 #define PRCM_LCDCLK_MGT                (0x044)
 #define PRCM_BMLCLK_MGT                (0x04C)
-#define PRCM_BML8580CLK_MGT    (0x108)
 #define PRCM_HSITXCLK_MGT      (0x050)
 #define PRCM_HSIRXCLK_MGT      (0x054)
 #define PRCM_HDMICLK_MGT       (0x058)

diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h
index b7ee8c9099081c2d6e0ac8db447e3501781d9bed..552a2d174f015958bbba9e8c26a6116cb0ccf1b4 100644 (file)
--- a/include/dt-bindings/mfd/dbx500-prcmu.h
+++ b/include/dt-bindings/mfd/dbx500-prcmu.h
@@ -61,24 +61,23 @@
 #define PRCMU_PLLSOC1                  43
 #define PRCMU_ARMSS            44
 #define PRCMU_PLLDDR           45
-#define PRCMU_BML8580CLK        46
 
 /* DSI Clocks */
-#define PRCMU_PLLDSI           47
-#define PRCMU_DSI0CLK          48
-#define PRCMU_DSI1CLK                  49
-#define PRCMU_DSI0ESCCLK       50
-#define PRCMU_DSI1ESCCLK       51
-#define PRCMU_DSI2ESCCLK       52
+#define PRCMU_PLLDSI           46
+#define PRCMU_DSI0CLK          47
+#define PRCMU_DSI1CLK                  48
+#define PRCMU_DSI0ESCCLK       49
+#define PRCMU_DSI1ESCCLK       50
+#define PRCMU_DSI2ESCCLK       51
 
 /* LCD DSI PLL - Ux540 only */
-#define PRCMU_PLLDSI_LCD        53
-#define PRCMU_DSI0CLK_LCD       54
-#define PRCMU_DSI1CLK_LCD       55
-#define PRCMU_DSI0ESCCLK_LCD    56
-#define PRCMU_DSI1ESCCLK_LCD    57
-#define PRCMU_DSI2ESCCLK_LCD    58
+#define PRCMU_PLLDSI_LCD        52
+#define PRCMU_DSI0CLK_LCD       53
+#define PRCMU_DSI1CLK_LCD       54
+#define PRCMU_DSI0ESCCLK_LCD    55
+#define PRCMU_DSI1ESCCLK_LCD    56
+#define PRCMU_DSI2ESCCLK_LCD    57
 
-#define PRCMU_NUM_CLKS         59
+#define PRCMU_NUM_CLKS         58
 
 #endif