MIPS: KVM: Fix 64-bit big endian dynamic translation

The MFC0 and MTC0 instructions in the guest which cause traps can be
replaced with 32-bit loads and stores to the commpage, however on big
endian 64-bit builds the offset needs to have 4 added so as to
load/store the least significant half of the long instead of the most
significant half.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/mips/kvm/dyntrans.c b/arch/mips/kvm/dyntrans.c
index 9a16ba2cb487927a09d3b337d7b02ed2b5e216a8..c793ff19a8a87ae3d65935b4bca5e441e2d2e156 100644 (file)
--- a/arch/mips/kvm/dyntrans.c
+++ b/arch/mips/kvm/dyntrans.c
@@ -103,6 +103,10 @@ int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
                mfc0_inst.i_format.rt = inst.c0r_format.rt;
                mfc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR |
                        offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
+#ifdef CONFIG_CPU_BIG_ENDIAN
+               if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8)
+                       mfc0_inst.i_format.simmediate |= 4;
+#endif
        }
 
        return kvm_mips_trans_replace(vcpu, opc, mfc0_inst);
@@ -121,6 +125,10 @@ int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
        mtc0_inst.i_format.rt = inst.c0r_format.rt;
        mtc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR |
                offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
+#ifdef CONFIG_CPU_BIG_ENDIAN
+       if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8)
+               mtc0_inst.i_format.simmediate |= 4;
+#endif
 
        return kvm_mips_trans_replace(vcpu, opc, mtc0_inst);
 }