Blackfin: MPU: handle caches for reserved memory

We weren't handling the user-specified cache behavior for the reserved
memory regions (via mem=/max_mem=).  The no-MPU code already takes care
of this, so add support to the MPU code as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index d4cc53a0ef89f136f70e1e5f945810d35490d133..7e6383dc7b2021003cbc9578aecb440ffde4541c 100644 (file)
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -131,7 +131,9 @@ static noinline int dcplb_miss(unsigned int cpu)
                } else
                        return CPLB_PROT_VIOL;
        } else if (addr >= _ramend) {
-           d_data |= CPLB_USER_RD | CPLB_USER_WR;
+               d_data |= CPLB_USER_RD | CPLB_USER_WR;
+               if (reserved_mem_dcache_on)
+                       d_data |= CPLB_L1_CHBL;
        } else {
                mask = current_rwx_mask[cpu];
                if (mask) {
@@ -231,6 +233,8 @@ static noinline int icplb_miss(unsigned int cpu)
                    return CPLB_PROT_VIOL;
        } else if (addr >= _ramend) {
                i_data |= CPLB_USER_RD;
+               if (reserved_mem_icache_on)
+                       i_data |= CPLB_L1_CHBL;
        } else {
                /*
                 * Two cases to distinguish - a supervisor access must