[Kane]:[user]: modify frame rate to 55fps for hix83112a and nov36672a

Change-Id: Ide2c3b2c12a1d7caf55f1003b6f807249023446b
Signed-off-by: xingbin <xingbin@huaqin.com>
Signed-off-by: tanhua1 <tanhua1@mt.com>
Reviewed-on: https://gerrit.mot.com/1314613
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
Submit-Approved: Jira Key

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-display-lcd.dtsi b/arch/arm64/boot/dts/exynos/exynos9610-display-lcd.dtsi
index d4801659377fd1909ee6e17340a54116c8e78891..a686edc8af6514e26a3237edcbc205e91d26df0e 100755 (executable)
--- a/arch/arm64/boot/dts/exynos/exynos9610-display-lcd.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610-display-lcd.dtsi
@@ -332,12 +332,12 @@
                                mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
                                resolution = <1080 2520>;
                                size = <64 148>;
-                               timing,refresh = <60>;
-                               timing,h-porch = <8 22 8>;
-                               timing,v-porch = <28 24 4>;
-                               timing,dsi-hs-clk = <1386>;
+                               timing,refresh = <55>;
+                               timing,h-porch = <18 34 8>;
+                               timing,v-porch = <5 27 5>;
+                               timing,dsi-hs-clk = <1284>;
                                /* TODO : pms value to be set */
-                               timing,pmsk = <5 533 1 0>;
+                               timing,pmsk = <4 395 1 0>;
                                timing,dsi-escape-clk = <10>;
                                mic_en = <0>;           /* 0: Disable, 1: Enable */
                                mic_ratio = <0>;        /* 0: 1/2 mic, 1: 1/3 mic */
@@ -368,12 +368,12 @@
                                mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
                                resolution = <1080 2520>;
                                size = <64 148>;
-                               timing,refresh = <60>;
-                               timing,h-porch = <40 40 20>;
+                               timing,refresh = <55>;
+                               timing,h-porch = <24 34 8>;
                                timing,v-porch = <8 10 2>;
-                               timing,dsi-hs-clk = <1440>;
+                               timing,dsi-hs-clk = <1284>;
                                /* TODO : pms value to be set */
-                               timing,pmsk = <4 443 1 0>;
+                               timing,pmsk = <4 395 1 0>;
                                timing,dsi-escape-clk = <10>;
                                mic_en = <0>;           /* 0: Disable, 1: Enable */
                                mic_ratio = <0>;        /* 0: 1/2 mic, 1: 1/3 mic */
@@ -384,7 +384,7 @@
                                dsc_slice_num = <0>;    /* count of dsc slice */
                                data_lane = <4>;        /* number of using data lane */
                                cmd_underrun_lp_ref = <4942>;   /* for underrun detect at command mode*/
-                               vt_compensation = <1>;  /* for underrun detect at video mode*/
+                               vt_compensation = <3>;  /* for underrun detect at video mode*/
                                mres_en = <0>;
                                mres_number = <3>;
                                mres_width = <1440 1080 720>;

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
index 2bc9add33dc10769702be32c863f38ade5bffa38..53917acb6da30b57ae955bbe61c5adeb9dcaa105 100755 (executable)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
@@ -204,6 +204,7 @@ const u32 dphy_timing[][10] = {
        {1310, 12, 22, 8, 9, 12, 9, 13, 9, 8},
        {1300, 12, 21, 8, 9, 12, 8, 13, 9, 7},
        {1290, 12, 21, 8, 9, 12, 8, 13, 9, 7},
+       {1284, 12, 21, 8, 9, 12, 8, 12, 9, 7},
        {1280, 12, 21, 8, 9, 12, 8, 12, 9, 7},
        {1270, 12, 21, 8, 9, 12, 8, 12, 9, 7},
        {1260, 12, 20, 8, 8, 12, 8, 12, 9, 7},
@@ -1276,33 +1277,39 @@ static int dsim_reg_wait_exit_ulps_state(u32 id)
 static int dsim_reg_get_dphy_timing(u32 hs_clk, u32 esc_clk,
                struct dphy_timing_value *t)
 {
-       int val;
+       u32 index = 0;
+       u32 timing_counts = sizeof(dphy_timing) / sizeof(dphy_timing[0]);
 
-       val  = (dphy_timing[0][0] - hs_clk) / 10;
+       for(index = 0;index < timing_counts;index++){
+               if(hs_clk==dphy_timing[index][0])
+                       break;
+       }
+       dsim_info("index = %d,timing_counts=%d.\n",index,timing_counts);
 
-       if (val > ((sizeof(dphy_timing) / sizeof(dphy_timing[0])) - 1)) {
+       if(index >= timing_counts){
                dsim_err("%u Mhz hs clock can't find proper dphy timing values\n",
                                hs_clk);
                return -EINVAL;
        }
 
+
        t->bps = hs_clk;
-       t->clk_prepare = dphy_timing[val][1];
-       t->clk_zero = dphy_timing[val][2];
-       t->clk_post = dphy_timing[val][3];
-       t->clk_trail = dphy_timing[val][4];
-       t->hs_prepare = dphy_timing[val][5];
-       t->hs_zero = dphy_timing[val][6];
-       t->hs_trail = dphy_timing[val][7];
-       t->lpx = dphy_timing[val][8];
-       t->hs_exit = dphy_timing[val][9];
-
-       dsim_dbg("%s: bps(%u) clk_prepare(%u) clk_zero(%u) clk_post(%u)\n",
+       t->clk_prepare = dphy_timing[index][1];
+       t->clk_zero = dphy_timing[index][2];
+       t->clk_post = dphy_timing[index][3];
+       t->clk_trail = dphy_timing[index][4];
+       t->hs_prepare = dphy_timing[index][5];
+       t->hs_zero = dphy_timing[index][6];
+       t->hs_trail = dphy_timing[index][7];
+       t->lpx = dphy_timing[index][8];
+       t->hs_exit = dphy_timing[index][9];
+
+       dsim_info("%s: bps(%u) clk_prepare(%u) clk_zero(%u) clk_post(%u)\n",
                        __func__, t->bps, t->clk_prepare, t->clk_zero,
                        t->clk_post);
-       dsim_dbg("clk_trail(%u) hs_prepare(%u) hs_zero(%u) hs_trail(%u)\n",
+       dsim_info("clk_trail(%u) hs_prepare(%u) hs_zero(%u) hs_trail(%u)\n",
                        t->clk_trail, t->hs_prepare, t->hs_zero, t->hs_trail);
-       dsim_dbg("lpx(%u) hs_exit(%u)\n", t->lpx, t->hs_exit);
+       dsim_info("lpx(%u) hs_exit(%u)\n", t->lpx, t->hs_exit);
 
        if ((esc_clk > 20) || (esc_clk < 7)) {
                dsim_err("%u Mhz cann't be used as escape clock\n", esc_clk);

diff --git a/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_lcd_ctrl.c b/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_lcd_ctrl.c
index dc48e295ffa06dfc615a6638c1f984ecb4c63563..fdaeb50a25e73618b6c68c3f35a14ea1cdeca61c 100755 (executable)
--- a/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_lcd_ctrl.c
+++ b/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_lcd_ctrl.c
@@ -72,19 +72,50 @@ void hix83112a_lcd_init(int id, struct decon_lcd *lcd)
 {
        if (dsim_wr_data(id, MIPI_DSI_DCS_LONG_WRITE, (unsigned long)SEQ_CMD_0,
                                ARRAY_SIZE(SEQ_CMD_0)) < 0)
-               dsim_err("fail to send SEQ_CMD_0 command.\n");
+       dsim_err("fail to send SEQ_CMD_0 command.\n");
        mdelay(1);
 
        if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
                                SEQ_CMD_1[0],
                                SEQ_CMD_1[1]) < 0)
-               dsim_err("fail to send SEQ_CMD_1 command.\n");
+       dsim_err("fail to send SEQ_CMD_1 command.\n");
        mdelay(1);
 
        if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
                                SEQ_CMD_2[0],
                                SEQ_CMD_2[1]) < 0)
-               dsim_err("fail to send SEQ_CMD_2 command.\n");
+       dsim_err("fail to send SEQ_CMD_2 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_LONG_WRITE, (unsigned long)SEQ_PASSWORD,
+               ARRAY_SIZE(SEQ_PASSWORD)) < 0)
+       dsim_err("fail to send SEQ_PASSWORD command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_LONG_WRITE, (unsigned long)SEQ_CMD_3,
+               ARRAY_SIZE(SEQ_CMD_3)) < 0)
+       dsim_err("fail to send SEQ_CMD_3 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_LONG_WRITE, (unsigned long)SEQ_CMD_4,
+               ARRAY_SIZE(SEQ_CMD_4)) < 0)
+       dsim_err("fail to send SEQ_CMD_4 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+               SEQ_CMD_5[0],
+               SEQ_CMD_5[1]) < 0)
+       dsim_err("fail to send SEQ_CMD_5 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_LONG_WRITE, (unsigned long)SEQ_CMD_6,
+               ARRAY_SIZE(SEQ_CMD_6)) < 0)
+       dsim_err("fail to send SEQ_CMD_6 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+               SEQ_CMD_7[0],
+               SEQ_CMD_7[1]) < 0)
+       dsim_err("fail to send SEQ_CMD_7 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_LONG_WRITE, (unsigned long)SEQ_OTP_DISABLE,
+               ARRAY_SIZE(SEQ_OTP_DISABLE)) < 0)
+       dsim_err("fail to send SEQ_OTP_DISABLE command.\n");
        mdelay(1);
 
        if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE, SEQ_SLEEP_OUT[0], 0) < 0)

diff --git a/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_param.h b/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_param.h
index 51df96d4e9d4a7632427e788fc8d83cf61da243a..70bf68ddbdd24f55027125a8b39067575fa5a617 100755 (executable)
--- a/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_param.h
+++ b/drivers/video/fbdev/exynos/dpu20/panels/hix83112a_param.h
@@ -46,5 +46,25 @@ static const unsigned char SEQ_CMD_1[] = {
 static const unsigned char SEQ_CMD_2[] = {
        0x55, 0x01
 };
-
+static const unsigned char SEQ_PASSWORD[] = {
+       0xB9, 0x83, 0x11, 0x2A
+};
+static const unsigned char SEQ_CMD_3[] = {
+       0xB2,0x00,0x02,0x00,0x90,0xD8,0x00,0x08,0x19,0xEE,0x11,0x01,0x00,0x15,0xA3,0x07
+};
+static const unsigned char SEQ_CMD_4[] = {
+       0xE7,0x0E,0x0E,0x1E,0x69,0x1C,0x69,0x00,0x50,0x02,0x02,0x00,0x00,0x02,0x02,0x02,0x05,0x14,0x14,0x32,0xB9,0x23,0xB9,0x08
+};
+static const unsigned char SEQ_CMD_5[] = {
+       0xE9,0xC3
+};
+static const unsigned char SEQ_CMD_6[] = {
+       0xCB,0xD1,0xDD
+};
+static const unsigned char SEQ_CMD_7[] = {
+       0xE9,0x3F
+};
+static const unsigned char SEQ_OTP_DISABLE[] = {
+       0xCF, 0x00, 0x14, 0x00, 0xC0
+};
 #endif /* __HIX83112A_PARAM_H__ */

diff --git a/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_lcd_ctrl.c b/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_lcd_ctrl.c
index 6b46fd36e0a8ca7c331f8ffb02b47505e893ede7..17fe550da608cf2d7002a8d7e8e57de1f17e2667 100755 (executable)
--- a/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_lcd_ctrl.c
+++ b/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_lcd_ctrl.c
@@ -70,6 +70,128 @@ struct decon_lcd nov36672a_lcd_info = {
  */
 void nov36672a_lcd_init(int id, struct decon_lcd *lcd)
 {
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_3[0],
+                               SEQ_CMD_3[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_3 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_4[0],
+                               SEQ_CMD_4[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_4 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_5[0],
+                               SEQ_CMD_5[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_5 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_6[0],
+                               SEQ_CMD_6[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_6 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_7[0],
+                               SEQ_CMD_7[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_7 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_8[0],
+                               SEQ_CMD_8[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_8 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_9[0],
+                               SEQ_CMD_9[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_9 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_10[0],
+                               SEQ_CMD_10[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_10 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_11[0],
+                               SEQ_CMD_11[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_11 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_12[0],
+                               SEQ_CMD_12[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_12 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_13[0],
+                               SEQ_CMD_13[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_13 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_14[0],
+                               SEQ_CMD_14[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_14 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_15[0],
+                               SEQ_CMD_15[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_15 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_16[0],
+                               SEQ_CMD_16[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_16 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_17[0],
+                               SEQ_CMD_17[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_17 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_18[0],
+                               SEQ_CMD_18[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_18 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_19[0],
+                               SEQ_CMD_19[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_19 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_20[0],
+                               SEQ_CMD_20[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_20 command.\n");
+       mdelay(1);
+
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_21[0],
+                               SEQ_CMD_21[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_21 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_22[0],
+                               SEQ_CMD_22[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_22 command.\n");
+       mdelay(1);
+       if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
+                               SEQ_CMD_23[0],
+                               SEQ_CMD_23[1]) < 0)
+               dsim_err("fail to send SEQ_CMD_23 command.\n");
+       mdelay(1);
 
        if (dsim_wr_data(id, MIPI_DSI_DCS_SHORT_WRITE_PARAM,
                                SEQ_CMD_0[0],

diff --git a/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_param.h b/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_param.h
index 02e31e2a54039e9a68b47c66fbba352fd4c3bf46..f20319dd3d6fe4b5e4f76bbcc83471d5c6bab71a 100755 (executable)
--- a/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_param.h
+++ b/drivers/video/fbdev/exynos/dpu20/panels/nov36672a_param.h
@@ -40,5 +40,78 @@ static const unsigned char SEQ_CMD_1[] = {
 static const unsigned char SEQ_CMD_2[] = {
        0x55, 0x01
 };
+static const unsigned char SEQ_CMD_3[] = {
+       0xFF, 0x20
+};
+static const unsigned char SEQ_CMD_4[] = {
+       0xFB, 0x01
+};
+
+static const unsigned char SEQ_CMD_5[] = {
+       0x62, 0xB8
+};
+static const unsigned char SEQ_CMD_6[] = {
+       0xFF, 0x24
+};
+static const unsigned char SEQ_CMD_7[] = {
+       0xFB, 0x01
+};
+
+static const unsigned char SEQ_CMD_8[] = {
+       0x92, 0x79
+};
+static const unsigned char SEQ_CMD_9[] = {
+       0xFF, 0x25
+};
+static const unsigned char SEQ_CMD_10[] = {
+       0xFB, 0x01
+};
+static const unsigned char SEQ_CMD_11[] = {
+       0x24, 0x79
+};
+
+static const unsigned char SEQ_CMD_12[] = {
+       0x25, 0x79
+};
+
+static const unsigned char SEQ_CMD_13[] = {
+       0x30, 0x30
+};
+
+static const unsigned char SEQ_CMD_14[] = {
+       0x38, 0x30
+};
+
+static const unsigned char SEQ_CMD_15[] = {
+       0x40, 0x63
+};
+
+static const unsigned char SEQ_CMD_16[] = {
+       0x4C, 0x63
+};
+static const unsigned char SEQ_CMD_17[] = {
+       0xFF, 0x26
+};
+static const unsigned char SEQ_CMD_18[] = {
+       0xFB, 0x01
+};
+static const unsigned char SEQ_CMD_19[] = {
+       0x19, 0x0B
+};
+
+static const unsigned char SEQ_CMD_20[] = {
+       0x1A, 0x16
+};
+
+static const unsigned char SEQ_CMD_21[] = {
+       0x1E, 0x99
+};
+static const unsigned char SEQ_CMD_22[] = {
+       0xFF, 0x10
+};
+static const unsigned char SEQ_CMD_23[] = {
+       0xFB, 0x01
+};
+
 
 #endif /* __NOV36672A_GAMMA_H__ */