struct str_MainHeader s_MainHeader;
struct str_DigitalInputHeader s_DigitalInputHeader;
struct str_DigitalOutputHeader s_DigitalOutputHeader;
- //struct str_TimerMainHeader s_TimerMainHeader,s_WatchdogMainHeader;
+ /* struct str_TimerMainHeader s_TimerMainHeader,s_WatchdogMainHeader; */
str_AnalogOutputHeader s_AnalogOutputHeader;
struct str_AnalogInputHeader s_AnalogInputHeader;
- // Read size
+ /* Read size */
s_MainHeader.w_HeaderSize =
w_EepromReadWord(w_PCIBoardEepromAddress, pc_PCIChipInformation,
0x100 + 8);
- // Read nbr of functionality
+ /* Read nbr of functionality */
w_Temp = w_EepromReadWord(w_PCIBoardEepromAddress,
pc_PCIChipInformation, 0x100 + 10);
s_MainHeader.b_Nfunctions = (unsigned char) w_Temp & 0x00FF;
- // Read functionality details
+ /* Read functionality details */
for (i = 0; i < s_MainHeader.b_Nfunctions; i++) {
- // Read Type
+ /* Read Type */
w_Temp = w_EepromReadWord(w_PCIBoardEepromAddress,
pc_PCIChipInformation, 0x100 + 12 + w_Count);
s_MainHeader.s_Functions[i].b_Type = (unsigned char) w_Temp & 0x3F;
w_Count = w_Count + 2;
- //Read Address
+ /* Read Address */
s_MainHeader.s_Functions[i].w_Address =
w_EepromReadWord(w_PCIBoardEepromAddress,
pc_PCIChipInformation, 0x100 + 12 + w_Count);
w_Count = w_Count + 2;
}
- // Display main header info
+ /* Display main header info */
for (i = 0; i < s_MainHeader.b_Nfunctions; i++) {
switch (s_MainHeader.s_Functions[i].b_Type) {
#include "../comedidev.h"
-// address scheme (page 2.17 of the manual)
+/* address scheme (page 2.17 of the manual) */
#define ADQ12B_SIZE 16
#define ADQ12B_CTREG 0x00
#define ADQ12B_CONT2 0x0e
#define ADQ12B_COWORD 0x0f
-// mask of the bit at STINR to check end of conversion
+/* mask of the bit at STINR to check end of conversion */
#define ADQ12B_EOC 0x20
#define TIMEOUT 20
-// available ranges through the PGA gains
+/* available ranges through the PGA gains */
static const struct comedi_lrange range_adq12b_ai_bipolar = { 4, {
BIP_RANGE(5),
BIP_RANGE(2),
.di_chans = 5,
.do_chans = 8
}
-// potentially, more adq-based deviced will be added
+/* potentially, more adq-based deviced will be added */
/*,
.name = "adq12b",
.ai_chans = 16, // this is just for reference, hardcoded again later
/* wait for end of convertion */
i = 0;
do {
-// comedi_udelay(1);
+/* comedi_udelay(1); */
status = inb(dev->iobase + ADQ12B_STINR);
status = status & ADQ12B_EOC;
} while (status == 0 && ++i < TIMEOUT);
-// } while (++i < 10);
+/* } while (++i < 10); */
/* read data */
hi = inb(dev->iobase + ADQ12B_ADHIG);
lo = inb(dev->iobase + ADQ12B_ADLOW);
- //rt_printk("debug: chan=%d range=%d status=%d hi=%d lo=%d\n", channel, range, status, hi, lo);
+ /* rt_printk("debug: chan=%d range=%d status=%d hi=%d lo=%d\n", channel, range, status, hi, lo); */
data[n] = (hi << 8) | lo;
}
*/
#define USE_DMA
-//#define DEBUG 1
-//#define DEBUG_FLAGS
+/* #define DEBUG 1 */
+/* #define DEBUG_FLAGS */
#include "../comedidev.h"
#define Waited (1<<5)
#define PrimaryTC (1<<6)
#define SecondaryTC (1<<7)
- //#define SerialRose
- //#define ReqRose
- //#define Paused
+ /* #define SerialRose */
+ /* #define ReqRose */
+ /* #define Paused */
#define Group_1_First_Clear 6 /* W */
#define Group_2_First_Clear 7 /* W */
#define DMA_Line_Control_Group1 76
#define DMA_Line_Control_Group2 108
-// channel zero is none
+/* channel zero is none */
static inline unsigned primary_DMAChannel_bits(unsigned channel)
{
return channel & 0x3;
struct comedi_async *async = s->async;
struct mite_struct *mite = devpriv->mite;
- //int i, j;
+ /* int i, j; */
long int AuxData = 0;
short data1 = 0;
short data2 = 0;
unsigned int m_status = 0;
unsigned long irq_flags;
- //interrupcions parasites
+ /* interrupcions parasites */
if (dev->attached == 0) {
- // assume it's from another card
+ /* assume it's from another card */
return IRQ_NONE;
}
ni_pcidio_print_flags(flags);
ni_pcidio_print_status(status);
- //printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf);
- //printk("buf[4096]=%08x\n",*(unsigned int *)(async->prealloc_buf+4096));
+ /* printk("buf[0]=%08x\n",*(unsigned int *)async->prealloc_buf); */
+ /* printk("buf[4096]=%08x\n",*(unsigned int *)(async->prealloc_buf+4096)); */
comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, irq_flags);
if (devpriv->di_mite_chan)
#ifdef MITE_DEBUG
mite_print_chsr(m_status);
#endif
- //printk("mite_bytes_transferred: %d\n",mite_bytes_transferred(mite,DI_DMA_CHAN));
- //mite_dump_regs(mite);
+ /* printk("mite_bytes_transferred: %d\n",mite_bytes_transferred(mite,DI_DMA_CHAN)); */
+ /* mite_dump_regs(mite); */
if (m_status & CHSR_INT) {
if (m_status & CHSR_LINKC) {
writel(CHOR_CLRLC,
flags &= IntEn;
if (flags & TransferReady) {
- //DPRINTK("TransferReady\n");
+ /* DPRINTK("TransferReady\n"); */
while (flags & TransferReady) {
work++;
if (work > 100) {
data2 = (AuxData & 0xffff0000) >> 16;
comedi_buf_put(async, data1);
comedi_buf_put(async, data2);
- //DPRINTK("read:%d, %d\n",data1,data2);
+ /* DPRINTK("read:%d, %d\n",data1,data2); */
flags = readb(devpriv->mite->daq_io_addr +
Group_1_Flags);
}
- //DPRINTK("buf_int_count: %d\n",async->buf_int_count);
- //DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",IntEn,flags,status);
- //ni_pcidio_print_flags(flags);
- //ni_pcidio_print_status(status);
+ /* DPRINTK("buf_int_count: %d\n",async->buf_int_count); */
+ /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",IntEn,flags,status); */
+ /* ni_pcidio_print_flags(flags); */
+ /* ni_pcidio_print_status(status); */
async->events |= COMEDI_CB_BLOCK;
}
flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
status = readb(devpriv->mite->daq_io_addr +
Interrupt_And_Window_Status);
- //DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,status=0x%02x\n",
- // IntEn,flags,status);
- //ni_pcidio_print_flags(flags);
- //ni_pcidio_print_status(status);
+ /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,status=0x%02x\n", */
+ /* IntEn,flags,status); */
+ /* ni_pcidio_print_flags(flags); */
+ /* ni_pcidio_print_status(status); */
}
out:
/* clear and enable interrupts */
writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
- //writeb(ClearExpired,devpriv->mite->daq_io_addr+Group_1_Second_Clear);
+ /* writeb(ClearExpired,devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
writeb(0x03,
if (cmd->stop_src == TRIG_NONE) {
devpriv->OpModeBits = DataLatching(0) | RunMode(7);
- } else { // TRIG_TIMER
+ } else { /* TRIG_TIMER */
devpriv->OpModeBits = Numbered | RunMode(7);
}
if (cmd->start_src == TRIG_NOW) {