ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller
authorTomasz Figa <t.figa@samsung.com>
Thu, 8 Jan 2015 06:54:34 +0000 (07:54 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 16 Jan 2015 14:35:41 +0000 (14:35 +0000)
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/boot/dts/exynos4210.dtsi
arch/arm/boot/dts/exynos4x12.dtsi

index bcc9e63c8070194f5c0ab4e88b729159911ae107..8e45ea44317e59a06a284b02fe75b5e702087883 100644 (file)
                reg = <0x10023CA0 0x20>;
        };
 
+       l2c: l2-cache-controller@10502000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x10502000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+               arm,tag-latency = <2 2 1>;
+               arm,data-latency = <2 2 1>;
+       };
+
        gic: interrupt-controller@10490000 {
                cpu-offset = <0x8000>;
        };
index 93b70402e9439a89184cbfffd816283cb4913eb1..8bc97c415c9a6f4dba7574b8adec446a172b23a5 100644 (file)
                reg = <0x10023CA0 0x20>;
        };
 
+       l2c: l2-cache-controller@10502000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x10502000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+               arm,tag-latency = <2 2 1>;
+               arm,data-latency = <3 2 1>;
+               arm,double-linefill = <1>;
+               arm,double-linefill-incr = <0>;
+               arm,double-linefill-wrap = <1>;
+               arm,prefetch-drop = <1>;
+               arm,prefetch-offset = <7>;
+       };
+
        clock: clock-controller@10030000 {
                compatible = "samsung,exynos4412-clock";
                reg = <0x10030000 0x20000>;