ARM: dts: Add hip01-ca9x2 dts file

Add dts file for Hisilicon hip01 ca9x2 board

Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
[olof: Folded in smp enable-method from a different patch]
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index f717c7b48603686a96f3c849b429259ba85d4feb..35b1bd49cfa1374358b14e7126ba480e602cf9ca 100644 (file)
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -9,6 +9,10 @@ HiP04 D01 Board
 Required root node properties:
        - compatible = "hisilicon,hip04-d01";
 
+HiP01 ca9x2 Board
+Required root node properties:
+       - compatible = "hisilicon,hip01-ca9x2";
+
 
 Hisilicon system controller
 
@@ -36,6 +40,27 @@ Example:
                reboot-offset = <0x4>;
        };
 
+-----------------------------------------------------------------------
+Hisilicon HiP01 system controller
+
+Required properties:
+- compatible : "hisilicon,hip01-sysctrl"
+- reg : Register address and size
+
+The HiP01 system controller is mostly compatible with hisilicon
+system controller,but it has some specific control registers for
+HIP01 SoC family, such as slave core boot, and also some same
+registers located at different offset.
+
+Example:
+
+       /* for hip01-ca9x2 */
+       sysctrl: system-controller@10000000 {
+               compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+               reg = <0x10000000 0x1000>;
+               reboot-offset = <0x4>;
+       };
+
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 31065cc01df3075b648e22f65eebdbc1a5236be7..293b80e196b7fec3ee460b6a915268c1be217d9e 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -123,6 +123,8 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \
 dtb-$(CONFIG_ARCH_HIGHBANK) += \
        highbank.dtb \
        ecx-2000.dtb
+dtb-$(CONFIG_ARCH_HIP01) += \
+       hip01-ca9x2.dtb
 dtb-$(CONFIG_ARCH_HIP04) += \
        hip04-d01.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += \

diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts
new file mode 100644 (file)
index 0000000..eca5e42
--- /dev/null
+++ b/arch/arm/boot/dts/hip01-ca9x2.dts
@@ -0,0 +1,51 @@
+/*
+ * Hisilicon Ltd. HiP01 SoC
+ *
+ * Copyright (C) 2014 Hisilicon Ltd.
+ * Copyright (C) 2014 Huawei Ltd.
+ *
+ * Author: Wang Long <long.wanglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/* First 8KB reserved for secondary core boot */
+/memreserve/ 0x80000000 0x00002000;
+
+#include "hip01.dtsi"
+
+/ {
+       model = "Hisilicon HIP01 Development Board";
+       compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "hisilicon,hip01-smp";
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <1>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x80000000>;
+       };
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
new file mode 100644 (file)
index 0000000..33130f8
--- /dev/null
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Hisilicon Ltd. HiP01 SoC
+ *
+ * Copyright (c) 2014 Hisilicon Ltd.
+ * Copyright (c) 2014 Huawei Ltd.
+ *
+ * Author: Wang Long <long.wanglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       gic: interrupt-controller@1e001000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
+       };
+
+       hisi_refclk144mhz: refclk144mkhz {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <144000000>;
+               clock-output-names = "hisi:refclk144khz";
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+               ranges = <0 0x10000000 0x20000000>;
+
+               amba {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "arm,amba-bus";
+                       ranges;
+
+                       uart0: uart@10001000 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x10001000 0x1000>;
+                               clocks = <&hisi_refclk144mhz>;
+                               clock-names = "apb_pclk";
+                               reg-shift = <2>;
+                               interrupts = <0 32 4>;
+                               status = "disabled";
+                       };
+
+                       uart1: uart@10002000 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x10002000 0x1000>;
+                               clocks = <&hisi_refclk144mhz>;
+                               clock-names = "apb_pclk";
+                               reg-shift = <2>;
+                               interrupts = <0 33 4>;
+                               status = "disabled";
+                       };
+
+                       uart2: uart@10003000 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x10003000 0x1000>;
+                               clocks = <&hisi_refclk144mhz>;
+                               clock-names = "apb_pclk";
+                               reg-shift = <2>;
+                               interrupts = <0 34 4>;
+                               status = "disabled";
+                       };
+
+                       uart3: uart@10006000 {
+                               compatible = "snps,dw-apb-uart";
+                               reg = <0x10006000 0x1000>;
+                               clocks = <&hisi_refclk144mhz>;
+                               clock-names = "apb_pclk";
+                               reg-shift = <2>;
+                               interrupts = <0 4 4>;
+                               status = "disabled";
+                       };
+               };
+
+               system-controller@10000000 {
+                       compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+                       reg = <0x10000000 0x1000>;
+                       reboot-offset = <0x4>;
+               };
+
+               global_timer@0a000200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0x0a000200 0x100>;
+                       interrupts = <1 11 0xf04>;
+                       clocks = <&hisi_refclk144mhz>;
+               };
+
+               local_timer@0a000600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x0a000600 0x100>;
+                       interrupts = <1 13 0xf04>;
+                       clocks = <&hisi_refclk144mhz>;
+               };
+       };
+};