clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
authorSean Wang <sean.wang@mediatek.com>
Fri, 5 May 2017 15:26:11 +0000 (23:26 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 20 Jun 2017 02:02:44 +0000 (19:02 -0700)
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mediatek/clk-mt8173.c
include/dt-bindings/clock/mt8173-clk.h

index 0ac3aee87726eb4ab9dbb083ce55e22a8e408266..96c292c3e440a3ca9ebf15039447209f58a01c61 100644 (file)
@@ -18,6 +18,7 @@
 
 #include "clk-mtk.h"
 #include "clk-gate.h"
+#include "clk-cpumux.h"
 
 #include <dt-bindings/clock/mt8173-clk.h>
 
@@ -525,6 +526,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
        "apll2_div5"
 };
 
+static const char * const ca53_parents[] __initconst = {
+       "clk26m",
+       "armca7pll",
+       "mainpll",
+       "univpll"
+};
+
+static const char * const ca57_parents[] __initconst = {
+       "clk26m",
+       "armca15pll",
+       "mainpll",
+       "univpll"
+};
+
+static const struct mtk_composite cpu_muxes[] __initconst = {
+       MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
+       MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
+};
+
 static const struct mtk_composite top_muxes[] __initconst = {
        /* CLK_CFG_0 */
        MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
@@ -948,6 +968,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
                                                clk_data);
        mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
 
+       mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+                                 clk_data);
+
        r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
        if (r)
                pr_err("%s(): could not register clock provider: %d\n",
index 6094bf7e50abb6146c18c013b49d93c7ab1f52ce..8aea623dd518e0e3571adf89f5866e4c520f4c42 100644 (file)
 #define CLK_INFRA_PMICSPI              10
 #define CLK_INFRA_PMICWRAP             11
 #define CLK_INFRA_CLK_13M              12
-#define CLK_INFRA_NR_CLK               13
+#define CLK_INFRA_CA53SEL               13
+#define CLK_INFRA_CA57SEL               14
+#define CLK_INFRA_NR_CLK                15
 
 /* PERI_SYS */