/* Structure to store I2C TPM specific stuff */
struct tpm_inf_dev {
struct i2c_client *client;
+ int locality;
u8 buf[TPM_BUFSIZE + sizeof(u8)]; /* max. buffer size + addr */
struct tpm_chip *chip;
enum i2c_chip_type chip_type;
if ((buf & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
- chip->vendor.locality = loc;
+ tpm_dev.locality = loc;
return loc;
}
u8 i = 0;
do {
- if (iic_tpm_read(TPM_STS(chip->vendor.locality), &buf, 1) < 0)
+ if (iic_tpm_read(TPM_STS(tpm_dev.locality), &buf, 1) < 0)
return 0;
i++;
{
/* this causes the current command to be aborted */
u8 buf = TPM_STS_COMMAND_READY;
- iic_tpm_write_long(TPM_STS(chip->vendor.locality), &buf, 1);
+ iic_tpm_write_long(TPM_STS(tpm_dev.locality), &buf, 1);
}
static ssize_t get_burstcount(struct tpm_chip *chip)
stop = jiffies + chip->vendor.timeout_d;
do {
/* Note: STS is little endian */
- if (iic_tpm_read(TPM_STS(chip->vendor.locality)+1, buf, 3) < 0)
+ if (iic_tpm_read(TPM_STS(tpm_dev.locality)+1, buf, 3) < 0)
burstcnt = 0;
else
burstcnt = (buf[2] << 16) + (buf[1] << 8) + buf[0];
if (burstcnt > (count - size))
burstcnt = count - size;
- rc = iic_tpm_read(TPM_DATA_FIFO(chip->vendor.locality),
+ rc = iic_tpm_read(TPM_DATA_FIFO(tpm_dev.locality),
&(buf[size]), burstcnt);
if (rc == 0)
size += burstcnt;
* so we sleep rather than keeping the bus busy
*/
usleep_range(SLEEP_DURATION_RESET_LOW, SLEEP_DURATION_RESET_HI);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, tpm_dev.locality, 0);
return size;
}
if (burstcnt > (len - 1 - count))
burstcnt = len - 1 - count;
- rc = iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality),
+ rc = iic_tpm_write(TPM_DATA_FIFO(tpm_dev.locality),
&(buf[count]), burstcnt);
if (rc == 0)
count += burstcnt;
}
/* write last byte */
- iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality), &(buf[count]), 1);
+ iic_tpm_write(TPM_DATA_FIFO(tpm_dev.locality), &(buf[count]), 1);
wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, &status);
if ((status & TPM_STS_DATA_EXPECT) != 0) {
rc = -EIO;
}
/* go and do it */
- iic_tpm_write(TPM_STS(chip->vendor.locality), &sts, 1);
+ iic_tpm_write(TPM_STS(tpm_dev.locality), &sts, 1);
return len;
out_err:
* so we sleep rather than keeping the bus busy
*/
usleep_range(SLEEP_DURATION_RESET_LOW, SLEEP_DURATION_RESET_HI);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, tpm_dev.locality, 0);
return rc;
}
return tpm_chip_register(chip);
out_release:
- release_locality(chip, chip->vendor.locality, 1);
+ release_locality(chip, tpm_dev.locality, 1);
tpm_dev.client = NULL;
out_err:
return rc;
struct tpm_chip *chip = tpm_dev.chip;
tpm_chip_unregister(chip);
- release_locality(chip, chip->vendor.locality, 1);
+ release_locality(chip, tpm_dev.locality, 1);
tpm_dev.client = NULL;
return 0;
struct priv_data {
void __iomem *iobase;
u16 manufacturer_id;
+ int locality;
int irq;
bool irq_tested;
wait_queue_head_t int_queue;
if ((ioread8(priv->iobase + TPM_ACCESS(l)) &
(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
- return chip->vendor.locality = l;
+ return priv->locality = l;
return -1;
}
struct priv_data *priv = chip->vendor.priv;
return ioread8(priv->iobase +
- TPM_STS(chip->vendor.locality));
+ TPM_STS(priv->locality));
}
static void tpm_tis_ready(struct tpm_chip *chip)
/* this causes the current command to be aborted */
iowrite8(TPM_STS_COMMAND_READY,
- priv->iobase + TPM_STS(chip->vendor.locality));
+ priv->iobase + TPM_STS(priv->locality));
}
static int get_burstcount(struct tpm_chip *chip)
stop = jiffies + chip->vendor.timeout_d;
do {
burstcnt = ioread8(priv->iobase +
- TPM_STS(chip->vendor.locality) + 1);
+ TPM_STS(priv->locality) + 1);
burstcnt += ioread8(priv->iobase +
- TPM_STS(chip->vendor.locality) +
+ TPM_STS(priv->locality) +
2) << 8;
if (burstcnt)
return burstcnt;
burstcnt = get_burstcount(chip);
for (; burstcnt > 0 && size < count; burstcnt--)
buf[size++] = ioread8(priv->iobase +
- TPM_DATA_FIFO(chip->vendor.
- locality));
+ TPM_DATA_FIFO(priv->locality));
}
return size;
}
out:
tpm_tis_ready(chip);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, priv->locality, 0);
return size;
}
burstcnt = get_burstcount(chip);
for (; burstcnt > 0 && count < len - 1; burstcnt--) {
iowrite8(buf[count], priv->iobase +
- TPM_DATA_FIFO(chip->vendor.locality));
+ TPM_DATA_FIFO(priv->locality));
count++;
}
/* write last byte */
iowrite8(buf[count],
- priv->iobase + TPM_DATA_FIFO(chip->vendor.locality));
+ priv->iobase + TPM_DATA_FIFO(priv->locality));
wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
&priv->int_queue, false);
status = tpm_tis_status(chip);
out_err:
tpm_tis_ready(chip);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, priv->locality, 0);
return rc;
}
intmask =
ioread32(priv->iobase +
- TPM_INT_ENABLE(chip->vendor.locality));
+ TPM_INT_ENABLE(priv->locality));
intmask &= ~TPM_GLOBAL_INT_ENABLE;
iowrite32(intmask,
- priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
+ priv->iobase + TPM_INT_ENABLE(priv->locality));
devm_free_irq(&chip->dev, priv->irq, chip);
priv->irq = 0;
chip->flags &= ~TPM_CHIP_FLAG_IRQ;
/* go and do it */
iowrite8(TPM_STS_GO,
- priv->iobase + TPM_STS(chip->vendor.locality));
+ priv->iobase + TPM_STS(priv->locality));
if (chip->flags & TPM_CHIP_FLAG_IRQ) {
ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
return len;
out_err:
tpm_tis_ready(chip);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, priv->locality, 0);
return rc;
}
goto out;
tpm_tis_ready(chip);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, priv->locality, 0);
itpm = true;
out:
itpm = rem_itpm;
tpm_tis_ready(chip);
- release_locality(chip, chip->vendor.locality, 0);
+ release_locality(chip, priv->locality, 0);
return rc;
}
int i;
interrupt = ioread32(priv->iobase +
- TPM_INT_STATUS(chip->vendor.locality));
+ TPM_INT_STATUS(priv->locality));
if (interrupt == 0)
return IRQ_NONE;
/* Clear interrupts handled with TPM_EOI */
iowrite32(interrupt,
priv->iobase +
- TPM_INT_STATUS(chip->vendor.locality));
- ioread32(priv->iobase + TPM_INT_STATUS(chip->vendor.locality));
+ TPM_INT_STATUS(priv->locality));
+ ioread32(priv->iobase + TPM_INT_STATUS(priv->locality));
return IRQ_HANDLED;
}
priv->irq = irq;
original_int_vec = ioread8(priv->iobase +
- TPM_INT_VECTOR(chip->vendor.locality));
+ TPM_INT_VECTOR(priv->locality));
iowrite8(irq,
- priv->iobase + TPM_INT_VECTOR(chip->vendor.locality));
+ priv->iobase + TPM_INT_VECTOR(priv->locality));
/* Clear all existing */
iowrite32(ioread32(priv->iobase +
- TPM_INT_STATUS(chip->vendor.locality)),
- priv->iobase + TPM_INT_STATUS(chip->vendor.locality));
+ TPM_INT_STATUS(priv->locality)),
+ priv->iobase + TPM_INT_STATUS(priv->locality));
/* Turn on */
iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
- priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
+ priv->iobase + TPM_INT_ENABLE(priv->locality));
priv->irq_tested = false;
*/
if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
iowrite8(original_int_vec,
- priv->iobase + TPM_INT_VECTOR(chip->vendor.locality));
+ priv->iobase + TPM_INT_VECTOR(priv->locality));
return 1;
}
int i;
original_int_vec = ioread8(priv->iobase +
- TPM_INT_VECTOR(chip->vendor.locality));
+ TPM_INT_VECTOR(priv->locality));
if (!original_int_vec) {
if (IS_ENABLED(CONFIG_X86))
static void tpm_tis_remove(struct tpm_chip *chip)
{
struct priv_data *priv = chip->vendor.priv;
- void __iomem *reg = priv->iobase +
- TPM_INT_ENABLE(chip->vendor.locality);
+ void __iomem *reg = priv->iobase + TPM_INT_ENABLE(priv->locality);
iowrite32(~TPM_GLOBAL_INT_ENABLE & ioread32(reg), reg);
- release_locality(chip, chip->vendor.locality, 1);
+ release_locality(chip, priv->locality, 1);
}
static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info,
/* Take control of the TPM's interrupt hardware and shut it off */
intmask = ioread32(priv->iobase +
- TPM_INT_ENABLE(chip->vendor.locality));
+ TPM_INT_ENABLE(priv->locality));
intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
intmask &= ~TPM_GLOBAL_INT_ENABLE;
iowrite32(intmask,
- priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
+ priv->iobase + TPM_INT_ENABLE(priv->locality));
if (request_locality(chip, 0) != 0) {
rc = -ENODEV;
/* Figure out the capabilities */
intfcaps =
ioread32(priv->iobase +
- TPM_INTF_CAPS(chip->vendor.locality));
+ TPM_INTF_CAPS(priv->locality));
dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
intfcaps);
if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
/* reenable interrupts that device may have lost or
BIOS/firmware may have disabled */
iowrite8(priv->irq, priv->iobase +
- TPM_INT_VECTOR(chip->vendor.locality));
+ TPM_INT_VECTOR(priv->locality));
intmask =
- ioread32(priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
+ ioread32(priv->iobase + TPM_INT_ENABLE(priv->locality));
intmask |= TPM_INTF_CMD_READY_INT
| TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
| TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
iowrite32(intmask,
- priv->iobase + TPM_INT_ENABLE(chip->vendor.locality));
+ priv->iobase + TPM_INT_ENABLE(priv->locality));
}
static int tpm_tis_resume(struct device *dev)