[COMMON] i2c: exynos5: I2C transfer sequence change for Clock changes
authorKyungwoo Kang <kwoo.kang@samsung.com>
Thu, 4 May 2017 04:50:21 +0000 (13:50 +0900)
committermyung-su.cha <myung-su.cha@samsung.com>
Wed, 9 May 2018 12:14:45 +0000 (21:14 +0900)
Transfer sequence has been changed for input clock. We no longer
wait until Master status IDLE between transfer and another transfer.
If we put SFR access or print log for debugging, it will increase
transfer latency.

Change-Id: I512adcbb7394e9566c535020e7aea29d23838188
Signed-off-by: Kyungwoo Kang <kwoo.kang@samsung.com>
drivers/i2c/busses/i2c-exynos5.c

index a97cf79cb23c90c2c08fff2886526ec5b168dd29..d3bf839226fdf5623e0d6922d15da40d7e0b8c53 100644 (file)
@@ -566,7 +566,6 @@ static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
                              struct i2c_msg *msgs, int stop)
 {
        unsigned long timeout;
-       unsigned long trans_status;
        unsigned long i2c_ctl;
        unsigned long i2c_auto_conf;
        unsigned long i2c_timeout;
@@ -675,21 +674,6 @@ static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
                                (&i2c->msg_complete, EXYNOS5_I2C_TIMEOUT);
 
                        ret = 0;
-                       if (i2c->scl_clk_stretch) {
-                               unsigned long timeout = jiffies + msecs_to_jiffies(100);
-
-                               do {
-                                       trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
-                                       if ((!(trans_status & HSI2C_MAST_ST_MASK)) ||
-                                          ((stop == 0) && (trans_status & HSI2C_MASTER_BUSY))){
-                                               timeout = 0;
-                                               break;
-                                       }
-                               } while(time_before(jiffies, timeout));
-
-                               if (timeout)
-                                       dev_err(i2c->dev, "SDA check timeout!!! = 0x%8lx\n",trans_status);
-                       }
                        disable_irq(i2c->irq);
 
                        if (i2c->trans_done < 0) {
@@ -757,25 +741,8 @@ static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
                                dev_err(i2c->dev, "ack was not received at write\n");
                                ret = i2c->trans_done;
                                exynos5_i2c_reset(i2c);
-                       } else {
-                               if (i2c->scl_clk_stretch) {
-                                       unsigned long timeout = jiffies + msecs_to_jiffies(100);
-
-                                       do {
-                                               trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
-                                               if ((!(trans_status & HSI2C_MAST_ST_MASK)) ||
-                                                  ((stop == 0) && (trans_status & HSI2C_MASTER_BUSY))){
-                                                       timeout = 0;
-                                                       break;
-                                               }
-                                       } while(time_before(jiffies, timeout));
-
-                                       if (timeout)
-                                               dev_err(i2c->dev, "SDA check timeout!!! = 0x%8lx\n",trans_status);
-                               }
-
+                       } else
                                ret = 0;
-                       }
                }
        }