drm/radeon: fixes for gfx clockgating on SI

Clockgating requires signalling between the CP and the
RLC to work properly.  Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks.  Removing the reset allows gfx
clockgating to work properly.  However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 3bd96cdb76013489b0780cae5af977755e1cf9e9..52fe0d4eeaa075e0b56d5f8d2402f114465754b9 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2338,7 +2338,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                switch (rdev->family) {
                case CHIP_TAHITI:
                        rdev->cg_flags =
-                               RADEON_CG_SUPPORT_GFX_MGCG |
+                               /*RADEON_CG_SUPPORT_GFX_MGCG |*/
                                RADEON_CG_SUPPORT_GFX_MGLS |
                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
                                RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2355,7 +2355,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                        break;
                case CHIP_PITCAIRN:
                        rdev->cg_flags =
-                               RADEON_CG_SUPPORT_GFX_MGCG |
+                               /*RADEON_CG_SUPPORT_GFX_MGCG |*/
                                RADEON_CG_SUPPORT_GFX_MGLS |
                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
                                RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2374,7 +2374,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                        break;
                case CHIP_VERDE:
                        rdev->cg_flags =
-                               RADEON_CG_SUPPORT_GFX_MGCG |
+                               /*RADEON_CG_SUPPORT_GFX_MGCG |*/
                                RADEON_CG_SUPPORT_GFX_MGLS |
                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
                                RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2395,7 +2395,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                        break;
                case CHIP_OLAND:
                        rdev->cg_flags =
-                               RADEON_CG_SUPPORT_GFX_MGCG |
+                               /*RADEON_CG_SUPPORT_GFX_MGCG |*/
                                RADEON_CG_SUPPORT_GFX_MGLS |
                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
                                RADEON_CG_SUPPORT_GFX_CGLS |
@@ -2413,7 +2413,7 @@ int radeon_asic_init(struct radeon_device *rdev)
                        break;
                case CHIP_HAINAN:
                        rdev->cg_flags =
-                               RADEON_CG_SUPPORT_GFX_MGCG |
+                               /*RADEON_CG_SUPPORT_GFX_MGCG |*/
                                RADEON_CG_SUPPORT_GFX_MGLS |
                                /*RADEON_CG_SUPPORT_GFX_CGCG |*/
                                RADEON_CG_SUPPORT_GFX_CGLS |

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index b1d22c704c537cebc236620912d02c9f489b309e..ff48c88c91335c5e78dfc68ce6ab503c88c0ca7a 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3371,17 +3371,6 @@ static int si_cp_resume(struct radeon_device *rdev)
        u32 rb_bufsz;
        int r;
 
-       /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
-       WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
-                                SOFT_RESET_PA |
-                                SOFT_RESET_VGT |
-                                SOFT_RESET_SPI |
-                                SOFT_RESET_SX));
-       RREG32(GRBM_SOFT_RESET);
-       mdelay(15);
-       WREG32(GRBM_SOFT_RESET, 0);
-       RREG32(GRBM_SOFT_RESET);
-
        WREG32(CP_SEM_WAIT_TIMER, 0x0);
        WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
 
@@ -4971,9 +4960,9 @@ static void si_enable_cgcg(struct radeon_device *rdev,
 
        orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
 
-       si_enable_gui_idle_interrupt(rdev, enable);
-
        if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
+               si_enable_gui_idle_interrupt(rdev, true);
+
                WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
 
                tmp = si_halt_rlc(rdev);
@@ -4990,6 +4979,8 @@ static void si_enable_cgcg(struct radeon_device *rdev,
 
                data |= CGCG_EN | CGLS_EN;
        } else {
+               si_enable_gui_idle_interrupt(rdev, false);
+
                RREG32(CB_CGTT_SCLK_CTRL);
                RREG32(CB_CGTT_SCLK_CTRL);
                RREG32(CB_CGTT_SCLK_CTRL);