clk:gcc-msm8916: add missing mss_q6_bimc_axi clock
authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Mon, 4 Jan 2016 11:01:53 +0000 (11:01 +0000)
committerStephen Boyd <sboyd@codeaurora.org>
Sat, 30 Jan 2016 00:35:22 +0000 (16:35 -0800)
This clock is required for loading the qdsp firmware.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/qcom/gcc-msm8916.c
include/dt-bindings/clock/qcom,gcc-msm8916.h

index e3bf09d7d0ef07f5672f9933dca6dd6896daff4c..899349b5aa07aa52d767c26dcbff7d540b560f2e 100644 (file)
@@ -2590,6 +2590,23 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
        },
 };
 
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+       .halt_reg = 0x49004,
+       .clkr = {
+               .enable_reg = 0x49004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mss_q6_bimc_axi_clk",
+                       .parent_names = (const char *[]){
+                               "bimc_ddr_clk_src",
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_oxili_ahb_clk = {
        .halt_reg = 0x59028,
        .clkr = {
@@ -3227,6 +3244,7 @@ static struct clk_regmap *gcc_msm8916_clocks[] = {
        [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
        [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
        [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
+       [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
 };
 
 static struct gdsc *gcc_msm8916_gdscs[] = {
index 257e2fbedd9466ff19d25169e394a847a5e5755b..28a27a4ed3c3c27e03dc04bfa13f03ee16d00d47 100644 (file)
 #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK         157
 #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK         158
 #define GCC_CODEC_DIGCODEC_CLK                 159
+#define GCC_MSS_Q6_BIMC_AXI_CLK                        160
 
 /* Indexes for GDSCs */
 #define BIMC_GDSC                              0