clk: qcom: mmcc-8960: Add DSI related clocks

Add rcg and branch clk structs for DSI1 and DSI2 blocks found in MSM8960
and APQ8064. Each DSI instance has 4 pairs of rcg and branch clocks.
Populate arrays mmcc_msm8960_clks and mmcc_apq8064_clks with these clocks.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index fa55e27dd9059dcf09645b43f738ac8bec93ef85..397f5df6422aa2f573b8090866581c95f9348684 100644 (file)
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -41,6 +41,10 @@ enum {
        P_PLL3,
        P_PLL15,
        P_HDMI_PLL,
+       P_DSI1_PLL_DSICLK,
+       P_DSI2_PLL_DSICLK,
+       P_DSI1_PLL_BYTECLK,
+       P_DSI2_PLL_BYTECLK,
 };
 
 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
@@ -85,6 +89,30 @@ static const char * const mmcc_pxo_pll8_pll2_pll3[] = {
        "pll3",
 };
 
+static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
+       { P_PXO, 0 },
+       { P_DSI2_PLL_DSICLK, 1 },
+       { P_DSI1_PLL_DSICLK, 3 },
+};
+
+static const char * const mmcc_pxo_dsi2_dsi1[] = {
+       "pxo",
+       "dsi2pll",
+       "dsi1pll",
+};
+
+static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
+       { P_PXO, 0 },
+       { P_DSI1_PLL_BYTECLK, 1 },
+       { P_DSI2_PLL_BYTECLK, 2 },
+};
+
+static const char * const mmcc_pxo_dsi1_dsi2_byte[] = {
+       "pxo",
+       "dsi1pllbyte",
+       "dsi2pllbyte",
+};
+
 static struct clk_pll pll2 = {
        .l_reg = 0x320,
        .m_reg = 0x324,
@@ -2042,6 +2070,350 @@ static struct clk_branch dsi2_s_ahb_clk = {
        },
 };
 
+static struct clk_rcg dsi1_src = {
+       .ns_reg = 0x0054,
+       .md_reg = 0x0050,
+       .mn = {
+               .mnctr_en_bit = 5,
+               .mnctr_reset_bit = 7,
+               .mnctr_mode_shift = 6,
+               .n_val_shift = 24,
+               .m_val_shift = 8,
+               .width = 8,
+       },
+       .p = {
+               .pre_div_shift = 14,
+               .pre_div_width = 2,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi2_dsi1_map,
+       },
+       .clkr = {
+               .enable_reg = 0x004c,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_src",
+                       .parent_names = mmcc_pxo_dsi2_dsi1,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_bypass2_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_branch dsi1_clk = {
+       .halt_reg = 0x01d0,
+       .halt_bit = 1,
+       .clkr = {
+               .enable_reg = 0x004c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_clk",
+                       .parent_names = (const char *[]){ "dsi1_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi2_src = {
+       .ns_reg = 0x012c,
+       .md_reg = 0x00a8,
+       .mn = {
+               .mnctr_en_bit = 5,
+               .mnctr_reset_bit = 7,
+               .mnctr_mode_shift = 6,
+               .n_val_shift = 24,
+               .m_val_shift = 8,
+               .width = 8,
+       },
+       .p = {
+               .pre_div_shift = 14,
+               .pre_div_width = 2,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi2_dsi1_map,
+       },
+       .clkr = {
+               .enable_reg = 0x003c,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_src",
+                       .parent_names = mmcc_pxo_dsi2_dsi1,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_bypass2_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_branch dsi2_clk = {
+       .halt_reg = 0x01d0,
+       .halt_bit = 2,
+       .clkr = {
+               .enable_reg = 0x003c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_clk",
+                       .parent_names = (const char *[]){ "dsi2_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi1_byte_src = {
+       .ns_reg = 0x00b0,
+       .p = {
+               .pre_div_shift = 12,
+               .pre_div_width = 4,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
+       },
+       .clkr = {
+               .enable_reg = 0x0090,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_byte_src",
+                       .parent_names = mmcc_pxo_dsi1_dsi2_byte,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_bypass2_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_branch dsi1_byte_clk = {
+       .halt_reg = 0x01cc,
+       .halt_bit = 21,
+       .clkr = {
+               .enable_reg = 0x0090,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_byte_clk",
+                       .parent_names = (const char *[]){ "dsi1_byte_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi2_byte_src = {
+       .ns_reg = 0x012c,
+       .p = {
+               .pre_div_shift = 12,
+               .pre_div_width = 4,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
+       },
+       .clkr = {
+               .enable_reg = 0x0130,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_byte_src",
+                       .parent_names = mmcc_pxo_dsi1_dsi2_byte,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_bypass2_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_branch dsi2_byte_clk = {
+       .halt_reg = 0x01cc,
+       .halt_bit = 20,
+       .clkr = {
+               .enable_reg = 0x00b4,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_byte_clk",
+                       .parent_names = (const char *[]){ "dsi2_byte_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi1_esc_src = {
+       .ns_reg = 0x0011c,
+       .p = {
+               .pre_div_shift = 12,
+               .pre_div_width = 4,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
+       },
+       .clkr = {
+               .enable_reg = 0x00cc,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_esc_src",
+                       .parent_names = mmcc_pxo_dsi1_dsi2_byte,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_esc_ops,
+               },
+       },
+};
+
+static struct clk_branch dsi1_esc_clk = {
+       .halt_reg = 0x01e8,
+       .halt_bit = 1,
+       .clkr = {
+               .enable_reg = 0x00cc,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_esc_clk",
+                       .parent_names = (const char *[]){ "dsi1_esc_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi2_esc_src = {
+       .ns_reg = 0x0150,
+       .p = {
+               .pre_div_shift = 12,
+               .pre_div_width = 4,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
+       },
+       .clkr = {
+               .enable_reg = 0x013c,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_esc_src",
+                       .parent_names = mmcc_pxo_dsi1_dsi2_byte,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_esc_ops,
+               },
+       },
+};
+
+static struct clk_branch dsi2_esc_clk = {
+       .halt_reg = 0x01e8,
+       .halt_bit = 3,
+       .clkr = {
+               .enable_reg = 0x013c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_esc_clk",
+                       .parent_names = (const char *[]){ "dsi2_esc_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi1_pixel_src = {
+       .ns_reg = 0x0138,
+       .md_reg = 0x0134,
+       .mn = {
+               .mnctr_en_bit = 5,
+               .mnctr_reset_bit = 7,
+               .mnctr_mode_shift = 6,
+               .n_val_shift = 16,
+               .m_val_shift = 8,
+               .width = 8,
+       },
+       .p = {
+               .pre_div_shift = 12,
+               .pre_div_width = 4,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi2_dsi1_map,
+       },
+       .clkr = {
+               .enable_reg = 0x0130,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi1_pixel_src",
+                       .parent_names = mmcc_pxo_dsi2_dsi1,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_pixel_ops,
+               },
+       },
+};
+
+static struct clk_branch dsi1_pixel_clk = {
+       .halt_reg = 0x01d0,
+       .halt_bit = 6,
+       .clkr = {
+               .enable_reg = 0x0130,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "mdp_pclk1_clk",
+                       .parent_names = (const char *[]){ "dsi1_pixel_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
+static struct clk_rcg dsi2_pixel_src = {
+       .ns_reg = 0x00e4,
+       .md_reg = 0x00b8,
+       .mn = {
+               .mnctr_en_bit = 5,
+               .mnctr_reset_bit = 7,
+               .mnctr_mode_shift = 6,
+               .n_val_shift = 16,
+               .m_val_shift = 8,
+               .width = 8,
+       },
+       .p = {
+               .pre_div_shift = 12,
+               .pre_div_width = 4,
+       },
+       .s = {
+               .src_sel_shift = 0,
+               .parent_map = mmcc_pxo_dsi2_dsi1_map,
+       },
+       .clkr = {
+               .enable_reg = 0x0094,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "dsi2_pixel_src",
+                       .parent_names = mmcc_pxo_dsi2_dsi1,
+                       .num_parents = 3,
+                       .ops = &clk_rcg_pixel_ops,
+               },
+       },
+};
+
+static struct clk_branch dsi2_pixel_clk = {
+       .halt_reg = 0x01d0,
+       .halt_bit = 19,
+       .clkr = {
+               .enable_reg = 0x0094,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "mdp_pclk2_clk",
+                       .parent_names = (const char *[]){ "dsi2_pixel_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+                       .flags = CLK_SET_RATE_PARENT,
+               },
+       },
+};
+
 static struct clk_branch gfx2d0_ahb_clk = {
        .hwcg_reg = 0x0038,
        .hwcg_bit = 28,
@@ -2325,6 +2697,8 @@ static struct clk_regmap *mmcc_msm8960_clks[] = {
        [CSI2_SRC] = &csi2_src.clkr,
        [CSI2_CLK] = &csi2_clk.clkr,
        [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
+       [DSI_SRC] = &dsi1_src.clkr,
+       [DSI_CLK] = &dsi1_clk.clkr,
        [CSI_PIX_CLK] = &csi_pix_clk.clkr,
        [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
        [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
@@ -2345,6 +2719,18 @@ static struct clk_regmap *mmcc_msm8960_clks[] = {
        [MDP_SRC] = &mdp_src.clkr,
        [MDP_CLK] = &mdp_clk.clkr,
        [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
+       [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
+       [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
+       [DSI2_SRC] = &dsi2_src.clkr,
+       [DSI2_CLK] = &dsi2_clk.clkr,
+       [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
+       [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
+       [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
+       [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
+       [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
+       [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
+       [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
+       [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
        [ROT_SRC] = &rot_src.clkr,
        [ROT_CLK] = &rot_clk.clkr,
        [TV_ENC_CLK] = &tv_enc_clk.clkr,
@@ -2359,6 +2745,8 @@ static struct clk_regmap *mmcc_msm8960_clks[] = {
        [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
        [VPE_SRC] = &vpe_src.clkr,
        [VPE_CLK] = &vpe_clk.clkr,
+       [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
+       [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
        [CAMCLK0_SRC] = &camclk0_src.clkr,
        [CAMCLK0_CLK] = &camclk0_clk.clkr,
        [CAMCLK1_SRC] = &camclk1_src.clkr,
@@ -2490,6 +2878,8 @@ static struct clk_regmap *mmcc_apq8064_clks[] = {
        [CSI2_SRC] = &csi2_src.clkr,
        [CSI2_CLK] = &csi2_clk.clkr,
        [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
+       [DSI_SRC] = &dsi1_src.clkr,
+       [DSI_CLK] = &dsi1_clk.clkr,
        [CSI_PIX_CLK] = &csi_pix_clk.clkr,
        [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
        [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
@@ -2506,6 +2896,18 @@ static struct clk_regmap *mmcc_apq8064_clks[] = {
        [MDP_SRC] = &mdp_src.clkr,
        [MDP_CLK] = &mdp_clk.clkr,
        [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
+       [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
+       [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
+       [DSI2_SRC] = &dsi2_src.clkr,
+       [DSI2_CLK] = &dsi2_clk.clkr,
+       [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
+       [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
+       [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
+       [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
+       [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
+       [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
+       [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
+       [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
        [ROT_SRC] = &rot_src.clkr,
        [ROT_CLK] = &rot_clk.clkr,
        [TV_DAC_CLK] = &tv_dac_clk.clkr,
@@ -2519,6 +2921,8 @@ static struct clk_regmap *mmcc_apq8064_clks[] = {
        [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
        [VPE_SRC] = &vpe_src.clkr,
        [VPE_CLK] = &vpe_clk.clkr,
+       [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
+       [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
        [CAMCLK0_SRC] = &camclk0_src.clkr,
        [CAMCLK0_CLK] = &camclk0_clk.clkr,
        [CAMCLK1_SRC] = &camclk1_src.clkr,