staging: sm750fb: rename PANEL_PLL_CTRL_* fields to PLL_CTRL_*

Several PLL control registers have the same layout and therefore the
field definitions may be shared for those registers. Renaming
definitions of PANEL_PLL_CTRL_* fields to more generic PLL_CTRL_* will
allow reusing these definitions for other PLL control registers.

Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c
index 940c43ffe78b954923357088fb6cf54a2124868e..277e5c55f9e7070cef30d1419f271f9df525eaea 100644 (file)
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -36,10 +36,10 @@ static unsigned int get_mxclk_freq(void)
                return MHz(130);
 
        pll_reg = PEEK32(MXCLK_PLL_CTRL);
-       M = FIELD_GET(pll_reg, PANEL_PLL_CTRL, M);
-       N = FIELD_GET(pll_reg, PANEL_PLL_CTRL, N);
-       OD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, OD);
-       POD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, POD);
+       M = FIELD_GET(pll_reg, PLL_CTRL, M);
+       N = FIELD_GET(pll_reg, PLL_CTRL, N);
+       OD = FIELD_GET(pll_reg, PLL_CTRL, OD);
+       POD = FIELD_GET(pll_reg, PLL_CTRL, POD);
 
        return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
 }
@@ -364,15 +364,15 @@ unsigned int formatPllReg(pll_value_t *pPLL)
         * applied to any PLL in the calling function.
         */
        reg =
-       FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF)
-       | FIELD_SET(0, PANEL_PLL_CTRL, POWER,  ON)
-       | FIELD_SET(0, PANEL_PLL_CTRL, INPUT,  OSC)
+       FIELD_SET(0, PLL_CTRL, BYPASS, OFF)
+       | FIELD_SET(0, PLL_CTRL, POWER,  ON)
+       | FIELD_SET(0, PLL_CTRL, INPUT,  OSC)
 #ifndef VALIDATION_CHIP
-       | FIELD_VALUE(0, PANEL_PLL_CTRL, POD,    pPLL->POD)
+       | FIELD_VALUE(0, PLL_CTRL, POD,    pPLL->POD)
 #endif
-       | FIELD_VALUE(0, PANEL_PLL_CTRL, OD,     pPLL->OD)
-       | FIELD_VALUE(0, PANEL_PLL_CTRL, N,      pPLL->N)
-       | FIELD_VALUE(0, PANEL_PLL_CTRL, M,      pPLL->M);
+       | FIELD_VALUE(0, PLL_CTRL, OD,     pPLL->OD)
+       | FIELD_VALUE(0, PLL_CTRL, N,      pPLL->N)
+       | FIELD_VALUE(0, PLL_CTRL, M,      pPLL->M);
 
        return reg;
 }

diff --git a/drivers/staging/sm750fb/ddk750_display.c b/drivers/staging/sm750fb/ddk750_display.c
index 1a29ae037ee3f7f5866d067d30ba2b2e90f65020..514f909217d5e98e164b3ebbdc542358343adba8 100644 (file)
--- a/drivers/staging/sm750fb/ddk750_display.c
+++ b/drivers/staging/sm750fb/ddk750_display.c
@@ -126,8 +126,8 @@ static void waitNextVerticalSync(int ctrl, int delay)
 
                /* Do not wait when the Primary PLL is off or display control is already off.
                   This will prevent the software to wait forever. */
-               if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
-                        PANEL_PLL_CTRL_POWER_OFF) ||
+               if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PLL_CTRL, POWER) ==
+                        PLL_CTRL_POWER_OFF) ||
                        (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
                         PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
                        return;

diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h
index a90b56f55f1ea28d78317a304d4fae341ef8a113..1ad8d554e2495c37644eede2c01924aba8502855 100644 (file)
--- a/drivers/staging/sm750fb/ddk750_reg.h
+++ b/drivers/staging/sm750fb/ddk750_reg.h
@@ -517,23 +517,23 @@
 #define PLL_CLK_COUNT_COUNTER                         15:0
 
 #define PANEL_PLL_CTRL                                0x00005C
-#define PANEL_PLL_CTRL_BYPASS                         18:18
-#define PANEL_PLL_CTRL_BYPASS_OFF                     0
-#define PANEL_PLL_CTRL_BYPASS_ON                      1
-#define PANEL_PLL_CTRL_POWER                          17:17
-#define PANEL_PLL_CTRL_POWER_OFF                      0
-#define PANEL_PLL_CTRL_POWER_ON                       1
-#define PANEL_PLL_CTRL_INPUT                          16:16
-#define PANEL_PLL_CTRL_INPUT_OSC                      0
-#define PANEL_PLL_CTRL_INPUT_TESTCLK                  1
+#define PLL_CTRL_BYPASS                               18:18
+#define PLL_CTRL_BYPASS_OFF                           0
+#define PLL_CTRL_BYPASS_ON                            1
+#define PLL_CTRL_POWER                                17:17
+#define PLL_CTRL_POWER_OFF                            0
+#define PLL_CTRL_POWER_ON                             1
+#define PLL_CTRL_INPUT                                16:16
+#define PLL_CTRL_INPUT_OSC                            0
+#define PLL_CTRL_INPUT_TESTCLK                        1
 #ifdef VALIDATION_CHIP
-    #define PANEL_PLL_CTRL_OD                         15:14
+    #define PLL_CTRL_OD                               15:14
 #else
-    #define PANEL_PLL_CTRL_POD                        15:14
-    #define PANEL_PLL_CTRL_OD                         13:12
+    #define PLL_CTRL_POD                              15:14
+    #define PLL_CTRL_OD                               13:12
 #endif
-#define PANEL_PLL_CTRL_N                              11:8
-#define PANEL_PLL_CTRL_M                              7:0
+#define PLL_CTRL_N                                    11:8
+#define PLL_CTRL_M                                    7:0
 
 #define CRT_PLL_CTRL                                  0x000060
 #define CRT_PLL_CTRL_BYPASS                           18:18