ARM: shmobile: r8a7794: add I2C DT support

Define the generic R8A7794 parts of the I2C[0-5] device nodes.

Based on the original patch by Koji Matsuoka <koji.matsuoka.xm@renesas.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index e0f32ede21814a82412391b893701e2747121474..7384db2a39925edb09eaee4f4eb2b816632ba0ee 100644 (file)
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -20,6 +20,12 @@
        #size-cells = <2>;
 
        aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
                spi0 = &qspi;
        };
 
@@ -502,6 +508,73 @@
                status = "disabled";
        };
 
+       /* The memory map in the User's Manual maps the cores to bus numbers */
+       i2c0: i2c@e6508000 {
+               compatible = "renesas,i2c-r8a7794";
+               reg = <0 0xe6508000 0 0x40>;
+               interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
+               power-domains = <&cpg_clocks>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@e6518000 {
+               compatible = "renesas,i2c-r8a7794";
+               reg = <0 0xe6518000 0 0x40>;
+               interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
+               power-domains = <&cpg_clocks>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@e6530000 {
+               compatible = "renesas,i2c-r8a7794";
+               reg = <0 0xe6530000 0 0x40>;
+               interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
+               power-domains = <&cpg_clocks>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@e6540000 {
+               compatible = "renesas,i2c-r8a7794";
+               reg = <0 0xe6540000 0 0x40>;
+               interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
+               power-domains = <&cpg_clocks>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c4: i2c@e6520000 {
+               compatible = "renesas,i2c-r8a7794";
+               reg = <0 0xe6520000 0 0x40>;
+               interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
+               power-domains = <&cpg_clocks>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c5: i2c@e6528000 {
+               compatible = "renesas,i2c-r8a7794";
+               reg = <0 0xe6528000 0 0x40>;
+               interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
+               power-domains = <&cpg_clocks>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
        mmcif0: mmc@ee200000 {
                compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
                reg = <0 0xee200000 0 0x80>;