}
pt = amdgpu_bo_gpu_offset(bo);
+ pt = amdgpu_gart_get_vm_pde(adev, pt);
if (parent->entries[pt_idx].addr == pt)
continue;
(count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
if (count) {
- uint64_t entry;
-
- entry = amdgpu_gart_get_vm_pde(adev, last_pt);
if (shadow)
amdgpu_vm_do_set_ptes(¶ms,
last_shadow,
- entry, count,
+ last_pt, count,
incr,
AMDGPU_PTE_VALID);
amdgpu_vm_do_set_ptes(¶ms, last_pde,
- entry, count, incr,
+ last_pt, count, incr,
AMDGPU_PTE_VALID);
}
}
if (count) {
- uint64_t entry;
-
- entry = amdgpu_gart_get_vm_pde(adev, last_pt);
-
if (vm->root.bo->shadow)
- amdgpu_vm_do_set_ptes(¶ms, last_shadow, entry,
+ amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt,
count, incr, AMDGPU_PTE_VALID);
- amdgpu_vm_do_set_ptes(¶ms, last_pde, entry,
+ amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt,
count, incr, AMDGPU_PTE_VALID);
}