#define SYSTEM_CTRL_PANEL_TRISTATE BIT(0)
#define MISC_CTRL 0x000004
-#define MISC_CTRL_DRAM_RERESH_COUNT 27:27
-#define MISC_CTRL_DRAM_RERESH_COUNT_1ROW 0
-#define MISC_CTRL_DRAM_RERESH_COUNT_3ROW 1
+#define MISC_CTRL_DRAM_RERESH_COUNT BIT(27)
#define MISC_CTRL_DRAM_REFRESH_TIME 26:25
#define MISC_CTRL_DRAM_REFRESH_TIME_8 0
#define MISC_CTRL_DRAM_REFRESH_TIME_16 1
#define MISC_CTRL_DRAM_REFRESH_TIME_32 2
#define MISC_CTRL_DRAM_REFRESH_TIME_64 3
-#define MISC_CTRL_INT_OUTPUT 24:24
-#define MISC_CTRL_INT_OUTPUT_NORMAL 0
-#define MISC_CTRL_INT_OUTPUT_INVERT 1
-#define MISC_CTRL_PLL_CLK_COUNT 23:23
-#define MISC_CTRL_PLL_CLK_COUNT_OFF 0
-#define MISC_CTRL_PLL_CLK_COUNT_ON 1
-#define MISC_CTRL_DAC_POWER 20:20
-#define MISC_CTRL_DAC_POWER_ON 0
-#define MISC_CTRL_DAC_POWER_OFF 1
-#define MISC_CTRL_CLK_SELECT 16:16
-#define MISC_CTRL_CLK_SELECT_OSC 0
-#define MISC_CTRL_CLK_SELECT_TESTCLK 1
+#define MISC_CTRL_INT_OUTPUT_INVERT BIT(24)
+#define MISC_CTRL_PLL_CLK_COUNT BIT(23)
+#define MISC_CTRL_DAC_POWER_OFF BIT(20)
+#define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16)
#define MISC_CTRL_DRAM_COLUMN_SIZE 15:14
#define MISC_CTRL_DRAM_COLUMN_SIZE_256 0
#define MISC_CTRL_DRAM_COLUMN_SIZE_512 1
#define MISC_CTRL_LOCALMEM_SIZE_16M 0
#define MISC_CTRL_LOCALMEM_SIZE_32M 1
#define MISC_CTRL_LOCALMEM_SIZE_64M 2
-#define MISC_CTRL_DRAM_TWTR 11:11
-#define MISC_CTRL_DRAM_TWTR_2CLK 0
-#define MISC_CTRL_DRAM_TWTR_1CLK 1
-#define MISC_CTRL_DRAM_TWR 10:10
-#define MISC_CTRL_DRAM_TWR_3CLK 0
-#define MISC_CTRL_DRAM_TWR_2CLK 1
-#define MISC_CTRL_DRAM_TRP 9:9
-#define MISC_CTRL_DRAM_TRP_3CLK 0
-#define MISC_CTRL_DRAM_TRP_4CLK 1
-#define MISC_CTRL_DRAM_TRFC 8:8
-#define MISC_CTRL_DRAM_TRFC_12CLK 0
-#define MISC_CTRL_DRAM_TRFC_14CLK 1
-#define MISC_CTRL_DRAM_TRAS 7:7
-#define MISC_CTRL_DRAM_TRAS_7CLK 0
-#define MISC_CTRL_DRAM_TRAS_8CLK 1
-#define MISC_CTRL_LOCALMEM_RESET 6:6
-#define MISC_CTRL_LOCALMEM_RESET_RESET 0
-#define MISC_CTRL_LOCALMEM_RESET_NORMAL 1
-#define MISC_CTRL_LOCALMEM_STATE 5:5
-#define MISC_CTRL_LOCALMEM_STATE_ACTIVE 0
-#define MISC_CTRL_LOCALMEM_STATE_INACTIVE 1
-#define MISC_CTRL_CPU_CAS_LATENCY 4:4
-#define MISC_CTRL_CPU_CAS_LATENCY_2CLK 0
-#define MISC_CTRL_CPU_CAS_LATENCY_3CLK 1
-#define MISC_CTRL_DLL 3:3
-#define MISC_CTRL_DLL_ON 0
-#define MISC_CTRL_DLL_OFF 1
-#define MISC_CTRL_DRAM_OUTPUT 2:2
-#define MISC_CTRL_DRAM_OUTPUT_LOW 0
-#define MISC_CTRL_DRAM_OUTPUT_HIGH 1
-#define MISC_CTRL_LOCALMEM_BUS_SIZE 1:1
-#define MISC_CTRL_LOCALMEM_BUS_SIZE_32 0
-#define MISC_CTRL_LOCALMEM_BUS_SIZE_64 1
-#define MISC_CTRL_EMBEDDED_LOCALMEM 0:0
-#define MISC_CTRL_EMBEDDED_LOCALMEM_ON 0
-#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF 1
+#define MISC_CTRL_DRAM_TWTR BIT(11)
+#define MISC_CTRL_DRAM_TWR BIT(10)
+#define MISC_CTRL_DRAM_TRP BIT(9)
+#define MISC_CTRL_DRAM_TRFC BIT(8)
+#define MISC_CTRL_DRAM_TRAS BIT(7)
+#define MISC_CTRL_LOCALMEM_RESET BIT(6)
+#define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5)
+#define MISC_CTRL_CPU_CAS_LATENCY BIT(4)
+#define MISC_CTRL_DLL_OFF BIT(3)
+#define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2)
+#define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1)
+#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0)
#define GPIO_MUX 0x000008
#define GPIO_MUX_31 31:31