drm/i915: pnv has a backlight polarity control bit, too

We already correctly ignore bit0 on gen < 4, now we also know why ;-)
I've decided that losing that single bit of precision isn't worth the
trouble to sprinkle IS_PINEVIEW checks all over the backlight control
code - that code is way too fragile imo.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dcc04f2143e1dc0d80c3520de5a471d67b38c2c..20244b971fc67b072c227b5cd92129371f4c6b4d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1828,6 +1828,8 @@
  */
 #define   BACKLIGHT_DUTY_CYCLE_SHIFT           (0)
 #define   BACKLIGHT_DUTY_CYCLE_MASK            (0xffff)
+#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV                (0xfffe)
+#define   BLM_POLARITY_PNV                     (1 << 0) /* pnv only */
 
 #define BLC_HIST_CTL           0x61260