i2c: designware-pcidrv: Add 10bit address feature to medfield/merrifield

Both Merrifield TRM and Medfield TRM state:
"Both 7-bit and 10-bit addressing modes are supported."

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 300802e75d2e3519bd86f76487cb8f48c5d4047f..d6423cfac588aa6621c86f788524bfda81cd93d7 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -141,6 +141,7 @@ static struct dw_pci_controller dw_pci_controllers[] = {
                .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
                .tx_fifo_depth = 32,
                .rx_fifo_depth = 32,
+               .functionality = I2C_FUNC_10BIT_ADDR,
                .clk_khz      = 25000,
                .setup = mfld_setup,
        },
@@ -149,6 +150,7 @@ static struct dw_pci_controller dw_pci_controllers[] = {
                .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
                .tx_fifo_depth = 64,
                .rx_fifo_depth = 64,
+               .functionality = I2C_FUNC_10BIT_ADDR,
                .scl_sda_cfg = &mrfld_config,
                .setup = mrfld_setup,
        },