dts: tvafe: update cutwindow for tl1 [1/1]
authorEvoke Zhang <evoke.zhang@amlogic.com>
Mon, 3 Jun 2019 03:28:28 +0000 (11:28 +0800)
committerTao Zeng <tao.zeng@amlogic.com>
Mon, 26 Aug 2019 08:14:50 +0000 (01:14 -0700)
PD#SWPL-8866

Problem:
atv line freq adjust is not qualified

Solution:
update cutwindow

Verify:
x301

Change-Id: Iaeaa2fbf27db22ad17ef2700e70f7af424a2539a
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts

index 6b8bf3b66adf18141ddd6d6a0c57ff4e5d3c4a11..c2d23d3e4a32aa5be6d844f0cb15bf3154fb79ed 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
                /* auto_adj_en:
                 * bit0 -- auto cdto
                 * bit1 -- auto hs
index 0f19f593f0f256d30be64ebf80ced160008c78c2..21db453d4a6fee7b6819aa1fd3d30c619cd91a30 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
                /* auto_adj_en:
                 * bit0 -- auto cdto
                 * bit1 -- auto hs
index 1ab9d7cbe898464ac246eef9447908b2c1e41928..a5594d98e6a88e329e1b75e2a90366dffdb078c6 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
        };
 
        vbi {
index 9dbe16ace0c17c578188497ed9a77d33ba09de38..4e049f4230351347555314422a7d69d94849199d 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
        };
 
        vbi {
index 10f449b51dd206cf9002459fe922ee7539810ede..690ee8b7e0a6728fb6e1d096b68141bb4a1c460d 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
                /* auto_adj_en:
                 * bit0 -- auto cdto
                 * bit1 -- auto hs
index 347ab375cb8db894cfcec5a010bd02b343715ed6..7c717e54619b734c8b9dbe69c33e612bc9a0e580 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
                /* auto_adj_en:
                 * bit0 -- auto cdto
                 * bit1 -- auto hs
index f4a4b1e27bf94f1a337839282198b8a43044a0bc..c61acf561a669e9ace9853ada684851a911ff0ea 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
        };
 
        vbi {
index fedae692c93654defa7c0c38cb49a5f90ac75a4b..65f63f90c310cfc772b468bb6cfccdaefa700c1b 100644 (file)
                clocks = <&clkc CLKID_DAC_CLK>;
                clock-names = "vdac_clk_gate";
 
-               cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
-               cutwindow_val_v = <4  8 14 16 24>;  /* level 0~4 */
+               cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
+               cutwindow_val_v = <4 8 14 16 24>;  /* level 0~4 */
        };
 
        vbi {