clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk

The register offset for the mipi-csi clk is off by 4, a copy paste
error from the mipi-dsi clk.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index ff0d621495fd38c01b1e94df02277aa5262bbf1d..79596463e0d94b66a3135e7fe60d07cfcd023ad3 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -633,7 +633,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
                                 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
                                 BIT(15), CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
-                                lcd_ch1_parents, 0x168, 0, 3, 8, 2,
+                                lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
                                 BIT(15), 0);
 
 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,