ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->color_logic_op = LOGIC_OPERATION_COPY;
ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->color_logic_op = LOGIC_OPERATION_COPY;
ge2d_cmd_cfg->hsc_rpt_p0_num = 1;
ge2d_cmd_cfg->vsc_rpt_l0_num = 1;
ge2d_cmd_cfg->hsc_div_en = 1;
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_cmd_cfg->hsc_adv_num =
+ ((dst_w - 1) < 1024) ? (dst_w - 1) : 0;
+#else
+ ge2d_cmd_cfg->hsc_adv_num = 0;
+#endif
} else {
ge2d_cmd_cfg->sc_hsc_en = 0;
ge2d_cmd_cfg->sc_vsc_en = 0;
ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
}
ge2d_cmd_cfg->color_blend_mode = (op >> 24) & 0xff;
ge2d_cmd_cfg->hsc_rpt_p0_num = 1;
ge2d_cmd_cfg->vsc_rpt_l0_num = 1;
ge2d_cmd_cfg->hsc_div_en = 1;
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_cmd_cfg->hsc_adv_num =
+ ((dst_w - 1) < 1024) ? (dst_w - 1) : 0;
+#else
+ ge2d_cmd_cfg->hsc_adv_num = 0;
+#endif
} else {
ge2d_cmd_cfg->sc_hsc_en = 0;
ge2d_cmd_cfg->sc_vsc_en = 0;
ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
}
ge2d_cmd_cfg->color_blend_mode = (op >> 24) & 0xff;
ge2d_cmd_cfg->hsc_rpt_p0_num = 1;
ge2d_cmd_cfg->vsc_rpt_l0_num = 1;
ge2d_cmd_cfg->hsc_div_en = 1;
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_cmd_cfg->hsc_adv_num =
+ ((dst_w - 1) < 1024) ? (dst_w - 1) : 0;
+#else
+ ge2d_cmd_cfg->hsc_adv_num = 0;
+#endif
} else {
ge2d_cmd_cfg->sc_hsc_en = 0;
ge2d_cmd_cfg->sc_vsc_en = 0;
ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
}
ge2d_cmd_cfg->color_blend_mode = (op >> 24) & 0xff;
ge2d_cmd_cfg->hsc_rpt_p0_num = 1;
ge2d_cmd_cfg->vsc_rpt_l0_num = 1;
ge2d_cmd_cfg->hsc_div_en = 1;
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_cmd_cfg->hsc_adv_num =
+ ((dst_w - 1) < 1024) ? (dst_w - 1) : 0;
+#else
+ ge2d_cmd_cfg->hsc_adv_num = 0;
+#endif
} else {
ge2d_cmd_cfg->sc_hsc_en = 0;
ge2d_cmd_cfg->sc_vsc_en = 0;
ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
}
ge2d_cmd_cfg->color_blend_mode = (op >> 24) & 0xff;
ge2d_cmd_cfg->hsc_rpt_p0_num = 0;
ge2d_cmd_cfg->vsc_rpt_l0_num = 0;
ge2d_cmd_cfg->hsc_div_en = 0;
+ ge2d_cmd_cfg->hsc_adv_num = 0;
ge2d_cmd_cfg->src1_fill_color_en = 1;
cfg->hsc_div_length = (124 << 24) / cfg->hsc_phase_step;
multo = cfg->hsc_phase_step * cfg->hsc_div_length;
+#ifndef CONFIG_GE2D_ADV_NUM
cfg->hsc_adv_num = multo >> 24;
+#endif
cfg->hsc_adv_phase = multo & 0xffffff;
}
(cfg->sc_vsc_en << 1) |
(cfg->sc_hsc_en << 0)), 11, 18);
- ge2d_reg_write(GE2D_HSC_ADV_CTRL,
- (cfg->hsc_adv_num << 24) |
- (cfg->hsc_adv_phase << 0)
- );
-
ge2d_reg_write(GE2D_HSC_START_PHASE_STEP, cfg->hsc_phase_step);
ge2d_reg_write(GE2D_HSC_PHASE_SLOPE, cfg->hsc_phase_slope);
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_reg_write(GE2D_HSC_ADV_CTRL,
+ (cfg->hsc_adv_num << 24) |
+ (cfg->hsc_adv_phase << 0)
+ );
+ if (cfg->hsc_adv_num > 255)
+ cfg->hsc_adv_num = cfg->hsc_adv_num >> 8;
ge2d_reg_write(GE2D_HSC_INI_CTRL,
(cfg->hsc_rpt_p0_num << 29) |
+ (cfg->hsc_adv_num << 24) |
(cfg->hsc_ini_phase << 0)
);
-
+#else
+ ge2d_reg_write(GE2D_HSC_ADV_CTRL,
+ (cfg->hsc_adv_num << 24) |
+ (cfg->hsc_adv_phase << 0)
+ );
+ ge2d_reg_write(GE2D_HSC_INI_CTRL,
+ (cfg->hsc_rpt_p0_num << 29) |
+ (cfg->hsc_ini_phase << 0)
+ );
+#endif
ge2d_reg_write(GE2D_VSC_START_PHASE_STEP, cfg->vsc_phase_step);
ge2d_cmd_cfg->hsc_rpt_p0_num = 1;
ge2d_cmd_cfg->vsc_rpt_l0_num = 1;
ge2d_cmd_cfg->hsc_div_en = 1;
-
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_cmd_cfg->hsc_adv_num =
+ ((dst_w - 1) < 1024) ? (dst_w - 1) : 0;
+#else
+ ge2d_cmd_cfg->hsc_adv_num = 0;
+#endif
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->color_logic_op = LOGIC_OPERATION_COPY;
ge2d_cmd_cfg->alpha_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->hsc_rpt_p0_num = 1;
ge2d_cmd_cfg->vsc_rpt_l0_num = 1;
ge2d_cmd_cfg->hsc_div_en = 1;
-
+#ifdef CONFIG_GE2D_ADV_NUM
+ ge2d_cmd_cfg->hsc_adv_num =
+ ((dst_w - 1) < 1024) ? (dst_w - 1) : 0;
+#else
+ ge2d_cmd_cfg->hsc_adv_num = 0;
+#endif
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->color_logic_op = LOGIC_OPERATION_COPY;
ge2d_cmd_cfg->alpha_blend_mode = OPERATION_LOGIC;
#define MAX_BITBLT_WORK_CONFIG 4
#define MAX_GE2D_CMD 32 /* 64 */
+/* #define CONFIG_GE2D_ADV_NUM */
#define CONFIG_GE2D_SRC2
#define GE2D_STATE_IDLE 0
#define GE2D_STATE_RUNNING 1