MIPS: devicetree: fix cpu interrupt controller node-names
authorAntony Pavlov <antonynpavlov@gmail.com>
Mon, 23 May 2016 11:39:00 +0000 (14:39 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 28 May 2016 10:35:12 +0000 (12:35 +0200)
Here is the quote from [1]:

    The unit-address must match the first address specified
    in the reg property of the node. If the node has no reg property,
    the @ and unit-address must be omitted and the node-name alone
    differentiates the node from other nodes at the same level

This patch adjusts MIPS dts-files and devicetree binding
documentation in accordance with [1].

    [1] Power.org(tm) Standard for Embedded Power Architecture(tm)
        Platform Requirements (ePAPR). Version 1.1 – 08 April 2011.
        Chapter 2.2.1.1 Node Name Requirements

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13345/
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Documentation/devicetree/bindings/mips/cpu_irq.txt
arch/mips/boot/dts/ingenic/jz4740.dtsi
arch/mips/boot/dts/ralink/mt7620a.dtsi
arch/mips/boot/dts/ralink/rt2880.dtsi
arch/mips/boot/dts/ralink/rt3050.dtsi
arch/mips/boot/dts/ralink/rt3883.dtsi
arch/mips/boot/dts/xilfpga/nexys4ddr.dts

index fc149f326dae11dec31a892ddda4f021e92a9db1..f080f06da6d89d8dc4c4751b5e8be4a392f9c7cd 100644 (file)
@@ -13,7 +13,7 @@ Required properties:
 - compatible : Should be "mti,cpu-interrupt-controller"
 
 Example devicetree:
-       cpu-irq: cpu-irq@0 {
+       cpu-irq: cpu-irq {
                #address-cells = <0>;
 
                interrupt-controller;
index 4a9c8f2a72d6b736f25a314e360412297dba69ac..f6ae6ed9c4b1a3849ab078c273c0afa199734d45 100644 (file)
@@ -5,7 +5,7 @@
        #size-cells = <1>;
        compatible = "ingenic,jz4740";
 
-       cpuintc: interrupt-controller@0 {
+       cpuintc: interrupt-controller {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
index 08bf24fefe9f5286692ccb184410de1ca7fffa9b..793c0c7ca921a29651c6e1205d1011624319f852 100644 (file)
@@ -9,7 +9,7 @@
                };
        };
 
-       cpuintc: cpuintc@0 {
+       cpuintc: cpuintc {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
index 182afde2f2e1cdf2688704b1db90199d4bb6f694..fb2faef0ab79a0cdb9a811de17151779be5d2193 100644 (file)
@@ -9,7 +9,7 @@
                };
        };
 
-       cpuintc: cpuintc@0 {
+       cpuintc: cpuintc {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
index e3203d414fee331eecce025924b0a8e7c4cee362..d3cb57f985da8fd1aa0332b40c186bec85a15d13 100644 (file)
@@ -9,7 +9,7 @@
                };
        };
 
-       cpuintc: cpuintc@0 {
+       cpuintc: cpuintc {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
index 3b131dd0d5ac29b9f728f435e4baf309e5affdd4..3d6fc9afdaf6f2c0ceb7a3ef70ff02aef75924f9 100644 (file)
@@ -9,7 +9,7 @@
                };
        };
 
-       cpuintc: cpuintc@0 {
+       cpuintc: cpuintc {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
index 686ebd11386d1412048e0c497fc11222b3620cb4..48d21127c3f38b2f575f6f7e96e038c3b2393f16 100644 (file)
@@ -10,7 +10,7 @@
                reg = <0x0 0x08000000>;
        };
 
-       cpuintc: interrupt-controller@0 {
+       cpuintc: interrupt-controller {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;