BUSWAIT is a 4-bit-wide value that controls the number of access waits
from the CPU to on-chip USB module. b'0000 inserts 0 wait (2 access
cycles) and b'1111 inserts 15 waits (17 access cycles, hardware
initial value), respectively.
BUSWAIT value depends on peripheral clock frequency supplied to on-chip
of each CPU, hence should be configurable through platform data.
Note that this patch assumes that b'0000 (0 wait, 2 access cycles) is
rerely used and considered as invalid. If valid 'buswait' data is not
provided by platform, initial b'1111 (15 waits, 17 access cycles) will
be applied as a safe default.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
if (r8a66597->pdata->on_chip) {
- r8a66597_bset(r8a66597, 0x04, SYSCFG1);
+ if (r8a66597->pdata->buswait)
+ r8a66597_write(r8a66597, r8a66597->pdata->buswait,
+ SYSCFG1);
+ else
+ r8a66597_write(r8a66597, 0x0f, SYSCFG1);
r8a66597_bset(r8a66597, HSE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
/* This callback can control port power instead of DVSTCTR register. */
void (*port_power)(int port, int power);
+ /* This parameter is for BUSWAIT */
+ u16 buswait;
+
/* set one = on chip controller, set zero = external controller */
unsigned on_chip:1;