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drm/i915/bdw: RPS frequency bits are the same as HSW
authorBen Widawsky <benjamin.widawsky@intel.com>
Tue, 1 Apr 2014 00:16:43 +0000 (17:16 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 1 Apr 2014 20:58:28 +0000 (22:58 +0200)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98abacd251bd2b0268520e77f92813dad135baea..cebe0d42a787290c183bf25f8f476821c3c6768a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3041,7 +3041,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
        if (val != dev_priv->rps.cur_freq) {
                gen6_set_rps_thresholds(dev_priv, val);
 
-               if (IS_HASWELL(dev))
+               if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                        I915_WRITE(GEN6_RPNSWREQ,
                                   HSW_FREQUENCY(val));
                else