pcie: fix check linkup timeout bug when pcie resume.
authorYue Wang <yue.wang@amlogic.com>
Mon, 9 Jul 2018 04:48:05 +0000 (12:48 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Mon, 9 Jul 2018 07:50:39 +0000 (00:50 -0700)
PD#169779: pcie: fix check linkup timeout bug when pcie resume.

Change-Id: Ia648c63447f101b71ae84dd960c0f414b80cbd32
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
drivers/amlogic/pci/pcie-amlogic-v2.c
drivers/amlogic/pci/pcie-amlogic.c
drivers/amlogic/pci/pcie-amlogic.h

index 530beabfa8e64790fd1685766362b1c51a813fd4..527ed2843b4933a040dcef85e84ba1993a09c07e 100644 (file)
@@ -554,8 +554,16 @@ static int amlogic_pcie_link_up(struct pcie_port *pp)
        u32   speed_okay = 0;
        u32   current_data_rate;
        int   cnt = 0;
+       u32   val = 0;
+       u32   linkup = 0;
        struct amlogic_pcie *amlogic_pcie = to_amlogic_pcie(pp);
 
+       val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+       linkup = ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+               (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
+       if (linkup)
+               return linkup;
+
        while (smlh_up == 0 || rdlh_up == 0
                || ltssm_up == 0 || speed_okay == 0) {
                udelay(20);
index 2ac3b05309f644d58bf004f4345644f9680f0100..9a5362f2d5ea0783eb5fe175eb0135604f6400d0 100644 (file)
@@ -514,8 +514,16 @@ int amlogic_pcie_link_up(struct pcie_port *pp)
        u32   speed_okay = 0;
        u32   current_data_rate;
        int   cnt = 0;
+       u32   val = 0;
+       u32   linkup = 0;
        struct amlogic_pcie *amlogic_pcie = to_amlogic_pcie(pp);
 
+       val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+       linkup = ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+               (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
+       if (linkup)
+               return linkup;
+
        while (smlh_up == 0 || rdlh_up == 0
                || ltssm_up == 0 || speed_okay == 0) {
                udelay(20);
index af537f0aea33d9c3456a5392e7a5ea84cb7fd51d..d3fca8199e3abf15d73a4ee8c92e776f74eece64 100644 (file)
 #define PCIE_CFG_STATUS12      0x30
 #define PCIE_CFG_STATUS17      0x44
 
+/* PCIe Port Logic registers */
+#define PLR_OFFSET                     0x700
+#define PCIE_PHY_DEBUG_R1              (PLR_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP      (0x1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING     (0x1 << 29)
+
 #define    WAIT_LINKUP_TIMEOUT         2000
 
 enum pcie_data_rate {