[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC
authorDave Jiang <djiang@mvista.com>
Thu, 10 May 2007 17:03:05 +0000 (10:03 -0700)
committerPaul Mackerras <paulus@samba.org>
Thu, 17 May 2007 11:10:16 +0000 (21:10 +1000)
Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices for MPC8540 ADS, MPC8548 CDS, and MPC8560 ADS.

Also fixed up the size of the PCI node on MPC8560 ADS.

Signed-off-by: Dave Jiang <djiang@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/mpc8540ads.dts
arch/powerpc/boot/dts/mpc8548cds.dts
arch/powerpc/boot/dts/mpc8560ads.dts

index f261d647ac856ac2dd25ee935ec934d1faddb530..d91e81c009f51863b23927850311783ed438775b 100644 (file)
                reg = <e0000000 00100000>;      // CCSRBAR 1M
                bus-frequency = <0>;
 
+               memory-controller@2000 {
+                       compatible = "fsl,8540-memory-controller";
+                       reg = <2000 1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <2 2>;
+               };
+
+               l2-cache-controller@20000 {
+                       compatible = "fsl,8540-l2-cache-controller";
+                       reg = <20000 1000>;
+                       cache-line-size = <20>; // 32 bytes
+                       cache-size = <40000>;   // L2, 256K
+                       interrupt-parent = <&mpic>;
+                       interrupts = <0 2>;
+               };
+
                i2c@3000 {
                        device_type = "i2c";
                        compatible = "fsl-i2c";
index b2b2200d0425302db75c1607d2f12b2fac62d0b0..ad96381033c09e7f35fbac9b4c3f83040ece2690 100644 (file)
                reg = <e0000000 00100000>;      // CCSRBAR 1M
                bus-frequency = <0>;
 
+               memory-controller@2000 {
+                       compatible = "fsl,8548-memory-controller";
+                       reg = <2000 1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <2 2>;
+               };
+
+               l2-cache-controller@20000 {
+                       compatible = "fsl,8548-l2-cache-controller";
+                       reg = <20000 1000>;
+                       cache-line-size = <20>; // 32 bytes
+                       cache-size = <80000>;   // L2, 512K
+                       interrupt-parent = <&mpic>;
+                       interrupts = <0 2>;
+               };
+
                i2c@3000 {
                        device_type = "i2c";
                        compatible = "fsl-i2c";
index 1f2afe9291d216a106ba13c82f0c91f1e0fb462f..80682152b0cf2314acbff0d8d9a51282a0fd7daa 100644 (file)
                reg = <e0000000 00000200>;
                bus-frequency = <13ab6680>;
 
+               memory-controller@2000 {
+                       compatible = "fsl,8540-memory-controller";
+                       reg = <2000 1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <2 2>;
+               };
+
+               l2-cache-controller@20000 {
+                       compatible = "fsl,8540-l2-cache-controller";
+                       reg = <20000 1000>;
+                       cache-line-size = <20>; // 32 bytes
+                       cache-size = <40000>;   // L2, 256K
+                       interrupt-parent = <&mpic>;
+                       interrupts = <0 2>;
+               };
+
                mdio@24520 {
                        device_type = "mdio";
                        compatible = "gianfar";
                        #address-cells = <3>;
                        compatible = "85xx";
                        device_type = "pci";
-                       reg = <8000 400>;
+                       reg = <8000 1000>;
                        clock-frequency = <3f940aa>;
                        interrupt-map-mask = <f800 0 0 7>;
                        interrupt-map = <