}
break;
+ case CSR_NODE_IDS:
+ if (tcode == TCODE_READ_QUADLET_REQUEST)
+ *data = cpu_to_be32(card->driver->
+ read_csr_reg(card, CSR_NODE_IDS));
+ else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
+ card->driver->write_csr_reg(card, CSR_NODE_IDS,
+ be32_to_cpu(*data));
+ else
+ rcode = RCODE_TYPE_ERROR;
+ break;
+
case CSR_CYCLE_TIME:
if (TCODE_IS_READ_REQUEST(tcode) && length == 4)
*data = cpu_to_be32(card->driver->
int node_id, int generation);
u32 (*read_csr_reg)(struct fw_card *card, int csr_offset);
+ void (*write_csr_reg)(struct fw_card *card, int csr_offset, u32 value);
struct fw_iso_context *
(*allocate_iso_context)(struct fw_card *card,
struct fw_ohci *ohci = fw_ohci(card);
switch (csr_offset) {
+ case CSR_NODE_IDS:
+ return reg_read(ohci, OHCI1394_NodeID) << 16;
+
case CSR_CYCLE_TIME:
return get_cycle_time(ohci);
}
}
+static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
+{
+ struct fw_ohci *ohci = fw_ohci(card);
+
+ switch (csr_offset) {
+ case CSR_NODE_IDS:
+ reg_write(ohci, OHCI1394_NodeID, value >> 16);
+ flush_writes(ohci);
+ break;
+
+ default:
+ WARN_ON(1);
+ break;
+ }
+}
+
static void copy_iso_headers(struct iso_context *ctx, void *p)
{
int i = ctx->header_length;
.cancel_packet = ohci_cancel_packet,
.enable_phys_dma = ohci_enable_phys_dma,
.read_csr_reg = ohci_read_csr_reg,
+ .write_csr_reg = ohci_write_csr_reg,
.allocate_iso_context = ohci_allocate_iso_context,
.free_iso_context = ohci_free_iso_context,