powerpc/885: set SDCR to 0x40

The MPC885 reference manual says that SDCR shall have value 0x40, but
most exemples set SDCR to 0x1
With 0x1 in SDCR, we observe TX underruns on SCC when using it in
QMC mode.
According the NXP technical support, this is a copy/paste error from
MPC860 reference manual, 0x40 being the only value supported
by the MPC885 HW.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>

diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 5e6ff38ea69f197a873e9f47923d9f3434107221..8ed65365be508848616843cea2f383a321942a8f 100644 (file)
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -228,7 +228,10 @@ void __init cpm_reset(void)
         * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
         */
        siu_conf = immr_map(im_siu_conf);
-       out_be32(&siu_conf->sc_sdcr, 1);
+       if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
+               out_be32(&siu_conf->sc_sdcr, 0x40);
+       else
+               out_be32(&siu_conf->sc_sdcr, 1);
        immr_unmap(siu_conf);
 
        cpm_muram_init();