PCI: designware: Parse bus-range property from devicetree

This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.

Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found.  We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.

[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index ed0d9b9fff2be5f5be5902554d0da70ed81591df..9f4faa8e8d005ee1810f0dc4272d63f4af3e17e6 100644 (file)
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -23,3 +23,6 @@ Required properties:
 
 Optional properties:
 - reset-gpio: gpio pin number of power good signal
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
+  specify this property, to keep backwards compatibility a range of 0x00-0xff
+  is assumed if not present)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 76d3d8e1f33bed4799c69a91fcb54acac8ed48c7..561fa30862aedf6fd23a396c646f8b1313e8aee8 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -500,6 +500,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
                }
        }
 
+       ret = of_pci_parse_bus_range(np, &pp->busn);
+       if (ret < 0) {
+               pp->busn.name = np->name;
+               pp->busn.start = 0;
+               pp->busn.end = 0xff;
+               pp->busn.flags = IORESOURCE_BUS;
+               dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
+                       ret, &pp->busn);
+       }
+
        if (!pp->dbi_base) {
                pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
                                        resource_size(&pp->cfg));
@@ -794,6 +804,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
 
        sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
        pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
+       pci_add_resource(&sys->resources, &pp->busn);
 
        return 1;
 }

diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 3e84e0ae08519a31b7b638689fd1521a6db40f58..a476e60993cb4c6ede387761ba906c29c751d1dd 100644 (file)
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -48,6 +48,7 @@ struct pcie_port {
        struct resource         cfg;
        struct resource         io;
        struct resource         mem;
+       struct resource         busn;
        struct pcie_port_info   config;
        int                     irq;
        u32                     lanes;