null_ether_addr);
} else {
/* resume tx fifos */
- if (!wlc_hw->wlc->tx_suspended)
- brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
-
+ brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
/* turn off PHYPLL to save power */
brcms_b_core_phypll_ctl(wlc_hw, false);
- /* remove gpio controls */
- if (wlc_hw->ucode_dbgsel)
- ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
-
wlc_hw->clk = false;
ai_core_disable(wlc_hw->sih, 0);
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
/* clear tx flow control */
brcms_c_txflowcontrol_reset(wlc);
- /* clear tx data fifo suspends */
- wlc->tx_suspended = false;
-
/* enable the RF Disable Delay timer */
W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
{
int i;
- /* Assume the device is there until proven otherwise */
- wlc->device_present = true;
/* Save our copy of the chanspec */
wlc->chanspec = ch20mhz_chspec(1);
u32 boardflags2; /* More board flags if sromrev >= 4 */
u32 machwcap; /* MAC capabilities */
u32 machwcap_backup; /* backup of machwcap */
- u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */
struct si_pub *sih; /* SI handle (cookie for siutils calls) */
char *vars; /* "environment" name=value */
u32 wake_override; /* bit flags to force MAC to WAKE mode */
u32 mute_override; /* Prevent ucode from sending beacons */
u8 etheraddr[ETH_ALEN]; /* currently configured ethernet address */
- u32 led_gpio_mask; /* LED GPIO Mask */
bool noreset; /* true= do not reset hw, used by WLC_OUT */
bool forcefastclk; /* true if h/w is forcing to use fast clk */
bool clk; /* core is out of reset and has clock */
bool sbclk; /* sb has clock */
- struct bmac_pmq *bmac_pmq; /* bmac PM states derived from ucode PMQ */
bool phyclk; /* phy is out of reset and has clock */
- bool dma_lpbk; /* core is in DMA loopback */
bool ucode_loaded; /* true after ucode downloaded */
* macintstatus: bit channel between isr and dpc.
* macintmask: sw runtime master macintmask value.
* defmacintmask: default "on" macintmask value.
- * device_present: (removable) device is present.
* clk: core is out of reset and has clock.
* core: pointer to active io core.
* band: pointer to active per-band state.
* corestate: per-core state (one per hw core).
* bandstate: per-band state (one per phy/radio).
* war16165: PCI slow clock 16165 war flag.
- * tx_suspended: data fifos need to remain suspended.
* txpend16165war: PCI slow clock 16165 war flag.
* qvalid: DirFrmQValid and BcMcFrmQValid.
* txpwr_local_max: regulatory local txpwr max.
struct brcms_hardware *hw;
/* clock */
- int clkreq_override;
u16 fastpwrup_dly;
/* interrupt */
u32 macintmask;
u32 defmacintmask;
- /* up and down */
- bool device_present;
-
bool clk;
/* multiband */
struct brcms_band *bandstate[MAXBANDS];
bool war16165;
-
- bool tx_suspended;
-
uint txpend16165war;
/* packet queue */