iwlegacy: cleanup/fix memory barriers

wmb(), rmb() are not needed when writel(), readl() are used as
accessors for MMIO. We use them indirectly via iowrite32(),
ioread32().

What is needed mmiowb(), for synchronizing writes coming from
different CPUs on PCIe bridge (see in patch comments). This
fortunately is not needed on x86, where mmiowb() is just
defined as compiler barrier. As iwlegacy devices are most likely
not used on anything other than x86, this is not so important
fix.

Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c
index 6dbd11f76f845a5b935d3e6b463d1d8f65909156..50308da8aee334f820d44c6a19ac1a4e84df6ad0 100644 (file)
--- a/drivers/net/wireless/iwlegacy/common.c
+++ b/drivers/net/wireless/iwlegacy/common.c
@@ -179,7 +179,6 @@ il_read_targ_mem(struct il_priv *il, u32 addr)
        _il_grab_nic_access(il);
 
        _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
-       rmb();
        value = _il_rd(il, HBUS_TARG_MEM_RDAT);
 
        _il_release_nic_access(il);
@@ -196,7 +195,6 @@ il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
        spin_lock_irqsave(&il->reg_lock, reg_flags);
        if (likely(_il_grab_nic_access(il))) {
                _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
-               wmb();
                _il_wr(il, HBUS_TARG_MEM_WDAT, val);
                _il_release_nic_access(il);
        }

diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index 1dfaa58acc456cf974baa638c743afcd85121577..df9b5b46283921e056f55c439c488d78bc8ba58a 100644 (file)
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -2146,6 +2146,13 @@ static inline void
 _il_release_nic_access(struct il_priv *il)
 {
        _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+       /*
+        * In above we are reading CSR_GP_CNTRL register, what will flush any
+        * previous writes, but still want write, which clear MAC_ACCESS_REQ
+        * bit, be performed on PCI bus before any other writes scheduled on
+        * different CPUs (after we drop reg_lock).
+        */
+       mmiowb();
 }
 
 static inline u32
@@ -2179,7 +2186,6 @@ static inline u32
 _il_rd_prph(struct il_priv *il, u32 reg)
 {
        _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
-       rmb();
        return _il_rd(il, HBUS_TARG_PRPH_RDAT);
 }
 
@@ -2187,7 +2193,6 @@ static inline void
 _il_wr_prph(struct il_priv *il, u32 addr, u32 val)
 {
        _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
-       wmb();
        _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
 }