radeon: Fix CP byte order on big endian architectures with KMS.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 8f41f701f0b7db8d9d65f2613a71cb54542b4270..64a692c0c31925dcabbc50bfb9f4e6e4ccb5f215 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -551,6 +551,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        /* cp setup */
        WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
        WREG32(RADEON_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+              RADEON_BUF_SWAP_32BIT |
+#endif
               REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
               REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
               REG_SET(RADEON_MAX_FETCH, max_fetch) |

diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 6d3d90406a244a97c541358b13528a212275bb38..e1b618574461b2a4659829a47f9ac986be37dc11 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -3184,6 +3184,7 @@
 #      define RADEON_RB_BUFSZ_MASK             (0x3f << 0)
 #      define RADEON_RB_BLKSZ_SHIFT            8
 #      define RADEON_RB_BLKSZ_MASK             (0x3f << 8)
+#      define RADEON_BUF_SWAP_32BIT            (1 << 17)
 #      define RADEON_MAX_FETCH_SHIFT           18
 #      define RADEON_MAX_FETCH_MASK            (0x3 << 18)
 #      define RADEON_RB_NO_UPDATE              (1 << 27)