[MIPS] cleanup struct irqaction initializers
authorThomas Gleixner <tglx@linutronix.de>
Tue, 28 Aug 2007 09:03:01 +0000 (09:03 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 11 Oct 2007 22:46:02 +0000 (23:46 +0100)
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
CC: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cobalt/irq.c
arch/mips/jmr3927/rbhma3100/irq.c
arch/mips/kernel/i8259.c
arch/mips/sgi-ip32/ip32-irq.c
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c

index 950ad1e8be444d7b68528102145bc45e68e8ce15..48763cd10eaae7a631f38b9b42bdf33bb86fe81f 100644 (file)
@@ -92,7 +92,9 @@ asmlinkage void plat_irq_dispatch(void)
 }
 
 static struct irqaction irq_via = {
-       no_action, 0, { { 0, } }, "cascade", NULL, NULL
+       .handler = no_action,
+       .mask = CPU_MASK_NONE,
+       .name = "cascade"
 };
 
 void __init arch_init_irq(void)
index d9efe692e551291332baeb824bcd18189fbfb778..3a47e8ce119616bb1fbc244eef8e6a86f4c9d59b 100644 (file)
@@ -104,7 +104,9 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction ioc_action = {
-       jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
+       .handler = jmr3927_ioc_interrupt,
+       .mask = CPU_MASK_NONE,
+       .name = "IOC",
 };
 
 static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
@@ -116,7 +118,9 @@ static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
        return IRQ_HANDLED;
 }
 static struct irqaction pcierr_action = {
-       jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
+       .handler = jmr3927_pcierr_interrupt,
+       .mask = CPU_MASK_NONE,
+       .name = "PCI error",
 };
 
 static void __init jmr3927_irq_init(void);
index 4f4359bfd180aefca57bfd12542cfd1369e0a719..60021647cac1db7d4221adb2c21ad4d28bc94c15 100644 (file)
@@ -303,7 +303,9 @@ void init_8259A(int auto_eoi)
  * IRQ2 is cascade interrupt to second interrupt controller
  */
 static struct irqaction irq2 = {
-       no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
+       .handler = no_action,
+       .mask = CPU_MASK_NONE,
+       .name = "cascade",
 };
 
 static struct resource pic1_io_resource = {
index fb9da9acf53f491004e9cabe3ee4a6dba25c70b9..5bad1b744d0f4bf262ded52658ec7d1a2f10968c 100644 (file)
@@ -117,10 +117,18 @@ static void inline flush_mace_bus(void)
 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
 
-struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
-                       CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
-struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED,
-                       CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
+struct irqaction memerr_irq = {
+       .handler = crime_memerr_intr,
+       .flags = IRQF_DISABLED,
+       .mask = CPU_MASK_NONE,
+       .name = "CRIME memory error",
+};
+struct irqaction cpuerr_irq = {
+       .handler = crime_cpuerr_intr,
+       .flags = IRQF_DISABLED,
+       .mask = CPU_MASK_NONE,
+       .name = "CRIME CPU error",
+};
 
 /*
  * For interrupts wired from a single device to the CPU.  Only the clock
index 9607ad5e734aff40681e710611efe69a30da78c5..551235648811c2de7597110561b21377f2357ae1 100644 (file)
@@ -243,10 +243,12 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
        return (sw_irq);
 }
 
-//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
-#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
-static struct irqaction toshiba_rbtx4927_irq_ioc_action =
-TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
+static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
+       .handler        = no_action,
+       .flags          = IRQF_SHARED,
+       .mask           = CPU_MASK_NONE,
+       .name           = TOSHIBA_RBTX4927_IOC_NAME
+};
 
 
 /**********************************************************************************/