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drm/dp: Add definition for Display Control DPCD Registers capability size
author
Yetunde Adebisi
<yetundex.adebisi@intel.com>
Tue, 5 Apr 2016 14:10:50 +0000
(15:10 +0100)
committer
Jani Nikula
<jani.nikula@intel.com>
Tue, 26 Apr 2016 12:03:09 +0000
(15:03 +0300)
This is used when reading Display Control capability Registers on the sink
device.
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link:
http://patchwork.freedesktop.org/patch/msgid/1459865452-9138-2-git-send-email-yetundex.adebisi@intel.com
include/drm/drm_dp_helper.h
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diff --git
a/include/drm/drm_dp_helper.h
b/include/drm/drm_dp_helper.h
index 1252108da0efcfafe809bfb955bf88a5e71ac965..92d9a5258e6db8b93eeab8697f200018427995cc 100644
(file)
--- a/
include/drm/drm_dp_helper.h
+++ b/
include/drm/drm_dp_helper.h
@@
-621,6
+621,7
@@
u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
+#define EDP_DISPLAY_CTL_CAP_SIZE 3
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);